Patents by Inventor Sheng Yao

Sheng Yao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230212278
    Abstract: Provided are a stable pharmaceutical composition of an anti-IL-17A antibody and an application thereof in medicine. The pharmaceutical composition contains an anti-IL-17A antibody or an antigen-binding fragment thereof, and a buffer, can further contain at least one stabilizer, and can further contain a surfactant.
    Type: Application
    Filed: June 9, 2021
    Publication date: July 6, 2023
    Inventors: Hongchuan Liu, Peixiang Liu, Jing Zhang, Jing Wang, Hui Liu, Yuanyuan Li, Hui Feng, Sheng Yao
  • Publication number: 20230207692
    Abstract: A semiconductor structure includes a substrate, a buried oxide layer formed in the substrate and near a surface of the substrate, a gate dielectric layer formed on the substrate and covering the buried oxide layer, a gate structure formed on the gate dielectric layer and overlapping the buried oxide layer, and a source region and a drain region formed in the substrate and at two sides of the gate structure.
    Type: Application
    Filed: March 2, 2023
    Publication date: June 29, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Sheng-Yao Huang, Yu-Ruei Chen, Zen-Jay Tsai, Yu-Hsiang Lin
  • Publication number: 20230192854
    Abstract: The present invention provides a stable pharmaceutical composition comprising an anti-BTLA (B and T lymphocyte attenuator) antibody and use thereof in medicines. The pharmaceutical composition comprises an anti-BTLA antibody and a buffer, further comprises at least one stabilizer, and optionally further comprises a surfactant.
    Type: Application
    Filed: July 18, 2022
    Publication date: June 22, 2023
    Inventors: Hongchuan Liu, Peixiang Liu, Jing Zhang, Yuehua Zhou, Hui Liu, Xueru Chen, Jing Wang, Hui Feng, Sheng Yao
  • Publication number: 20230178657
    Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.
    Type: Application
    Filed: January 31, 2023
    Publication date: June 8, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ming Lai, Yen-Chen Chen, Jen-Po Huang, Sheng-Yao Huang, Hui-Ling Chen, Qinggang Xing, Ding-Lung Chen, Li Li Ding, Yao-Hung Liu
  • Publication number: 20230159632
    Abstract: The present invention provides an antibody or a functional fragment thereof that specifically binds to IL-17A with high affinity. Also provided are a nucleic acid molecule encoding the antibody or the functional fragment thereof disclosed herein, an expression vector and a host cell for expressing the antibody or the functional fragment thereof disclosed herein, and a method for preparing the antibody or the functional fragment thereof disclosed herein. The present invention also provides a pharmaceutical composition comprising the antibody or the functional fragment thereof disclosed herein, and use of the antibody or the functional fragment thereof disclosed herein for treating an immune dysfunction disease.
    Type: Application
    Filed: December 11, 2019
    Publication date: May 25, 2023
    Inventors: Jian Yao, Dan Meng, Hui Feng, Sheng Yao, Hai Wu
  • Publication number: 20230142514
    Abstract: A dredging device for dredging a pipe is provided including: a carrying frame, adapted to connected to a pipe; a shaking dredging unit including a first shaking plate and a second shaking plate, and the first shaking plate and the second shaking plate are arranged within the pipe; and a driving unit, connected to the carrying frame. The driving unit is connected to the first shaking plate and the second shaking plate for driving the first shaking plate and the second shaking plate to reciprocate to approach or move away from each other.
    Type: Application
    Filed: December 30, 2022
    Publication date: May 11, 2023
    Inventors: Min CHEN, Xiaohua WANG, Baokang CHEN, Junwu ZHAO, Zhenfeng MEI, Xiaolei XUE, Xiaomin PENG, Shengjie YU, Ruipeng LIU, Peng ZHAO, Yiwen DING, Jinyong ZHU, Sheng YAO, Zhucheng WANG, Hao LIANG, Hui WANG
  • Publication number: 20230129670
    Abstract: Disclosed are a resource allocation method and a system, a terminal device, and a network device. The method includes: sending a message carrying a terminal type of a terminal device to a network device; and receiving resource allocation information of the terminal device, sent by the network device, the resource allocation information being obtained by the network device according to the terminal type. The terminal device can actively report the terminal type to the network device, such that the network device can perform rational resource allocation on the terminal device according to the terminal type, thereby reducing the waste of network resources and improving the rationality of terminal services.
    Type: Application
    Filed: December 23, 2022
    Publication date: April 27, 2023
    Applicant: GUANGDONG GENIUS TECHNOLOGY CO., LTD.
    Inventor: Sheng YAO
  • Publication number: 20230130963
    Abstract: Disclosed by embodiments of the present disclosure are a method for processing a relax measurement parameter update, a terminal device, and a computer-readable storage medium. When a network device changes a relax measurement configuration parameter in system information, the terminal device may still independently determine the use of a new relax measurement configuration parameter according to its own conditions, which perfects protocol implementation and allows the terminal device to have more reasonable performance.
    Type: Application
    Filed: December 22, 2022
    Publication date: April 27, 2023
    Applicant: GUANGDONG GENIUS TECHNOLOGY CO., LTD.
    Inventor: Sheng YAO
  • Publication number: 20230131821
    Abstract: A heat dissipation structure, includes: a lead frame, including a high temperature pad and a low temperature pad, the high temperature pad and the low temperature pad being two portions in the lead frame which are separated from each other, wherein a high heat generation component is disposed on the high temperature pad; and a high thermal conduction element, including two sides which are respectively directly connected with the high temperature pad and the low temperature pad, to dissipate the heat energy from the high heat generation component to the low temperature pad.
    Type: Application
    Filed: July 6, 2022
    Publication date: April 27, 2023
    Inventors: Heng-Chi Huang, Sheng-Yao Wu, Chi-Yung Wu, Yong-Zhong Hu
  • Patent number: 11631771
    Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: April 18, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ming Lai, Yen-Chen Chen, Jen-Po Huang, Sheng-Yao Huang, Hui-Ling Chen, Qinggang Xing, Ding-Lung Chen, Li Li Ding, Yao-Hung Liu
  • Publication number: 20230113265
    Abstract: A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive bump over and electrically connected to the chip. The chip package structure includes a ring-like structure over and electrically insulated from the chip. The ring-like structure surrounds the conductive bump, and the ring-like structure and the conductive bump are made of a same material.
    Type: Application
    Filed: December 13, 2022
    Publication date: April 13, 2023
    Inventors: Sheng-Yao YANG, Ling-Wei LI, Yu-Jui WU, Cheng-Lin HUANG, Chien-Chen LI, Lieh-Chuan CHEN, Che-Jung CHU, Kuo-Chio LIU
  • Patent number: 11626515
    Abstract: A semiconductor structure includes a substrate, a buried oxide layer formed in the substrate and near a surface of the substrate, a gate dielectric layer formed on the substrate and covering the buried oxide layer, a gate structure formed on the gate dielectric layer and overlapping the buried oxide layer, and a source region and a drain region formed in the substrate and at two sides of the gate structure.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: April 11, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Sheng-Yao Huang, Yu-Ruei Chen, Zen-Jay Tsai, Yu-Hsiang Lin
  • Publication number: 20230107856
    Abstract: The present disclosure relates to use of an anti-PD-1 antibody and/or an antigen-binding fragment thereof in the treatment of a malignancy. In particular, the present disclosure relates to use of an anti-PD-1 antibody and/or an antigen-binding fragment thereof in the treatment of a sarcoma, alveolar soft part sarcoma, angiosarcoma and undifferentiated polymorphic sarcoma, and use of an anti-PD-1 antibody and/or an antigen-binding fragment thereof in the treatment of lymphoma.
    Type: Application
    Filed: February 5, 2021
    Publication date: April 6, 2023
    Inventors: Sheng YAO, Hui FENG, Hai WU
  • Publication number: 20230082898
    Abstract: The present disclosure relates to use of an anti-PD-1 antibody in the treatment of melanoma. The present disclosure also relates to use of an agent for detecting BRAF, NRAS, and CDK4/CCND1 gene mutations in a detection kit for predicting the therapeutic effect of an anti-PD-1 antibody and/or an antigen-binding fragment thereof administered alone to a patient with melanoma.
    Type: Application
    Filed: February 10, 2021
    Publication date: March 16, 2023
    Inventors: Sheng YAO, Hui Feng, Hai Wu
  • Publication number: 20230071664
    Abstract: Disclosed is a cell measurement method based on frequency point optimization. The method includes: when a cell measurement condition is satisfied, if a current serving cell of a terminal device matches a serving cell in a stored measurement record, measuring cell information of a frequency point corresponding to the highest measurement priority in the measurement record. When the cell measurement condition is satisfied and the current serving cell of the terminal device does not match a serving cell in the measurement record, if the current serving cell is a cell corresponding to the frequency point corresponding to the highest measurement priority in the measurement record, measuring cell information of the frequency point corresponding to the highest measurement priority in the measurement record.
    Type: Application
    Filed: November 17, 2022
    Publication date: March 9, 2023
    Applicant: GUANGDONG GENIUS TECHNOLOGY CO., LTD.
    Inventor: Sheng YAO
  • Publication number: 20230073183
    Abstract: Provided are an improved uricase, a method for treating hyperuricemia using the same, and a corresponding pharmaceutical composition. The improved uricase comprises an amino acid sequence having at least about 90% identity with SEQ ID NO: 1, wherein the sequence is not SEQ ID NO: 1.
    Type: Application
    Filed: October 10, 2020
    Publication date: March 9, 2023
    Inventors: GUOFENG HUANG, Peng ZHAO, SI CHEN, TIE LI, RUISHENG LI, JING ZHANG, YUEHUA ZHOU, HONGCHUAN LIU, SHENG YAO
  • Patent number: 11567745
    Abstract: A compiler includes a front-end module, an optimization module, and a back-end module. The front-end module pre-processes a source code to generate an intermediate code. The optimization module optimizes the intermediate code. The back-end module translates the optimized intermediate code to generate a machine code. Optimization includes translating a branch instruction in the intermediate code into performing the following operations: establishing a post dominator tree for the branch instruction to find an immediate post dominator of the branch instruction as a reconverge point of a first path and a second path of the branch instruction; inserting a specific instruction at the front end of the reconverge point, so as to jumping to execute the instructions of the second path on the condition that once the specific instruction on the first path is executed.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: January 31, 2023
    Inventors: Chung-ho Chen, Dun-jie Chen, Feng-ming Hsu, Sheng-yao Lin
  • Publication number: 20230019098
    Abstract: There are provided bivalent compounds and conjugates thereof, the conjugates comprising a bivalent compound, a targeting moiety, and a bioactive agent, as well as pharmaceutical compositions and methods of use of the conjugate for the treatment, inhibition, or prevention of diseases and disorders which are therapeutic targets of the bioactive agent.
    Type: Application
    Filed: June 20, 2022
    Publication date: January 19, 2023
    Inventors: Jiasheng LV, Haixiao SIYANG, Yijie YIN, Wantao GUO, Haiming LI, Dawei CHEN, Jiamin GU, Xianqi KONG, Jun PAN, Xinxin MA, Peiming SONG, Chun WU, Hui FENG, Sheng YAO
  • Publication number: 20230006048
    Abstract: A high-voltage transistor device includes a semiconductor substrate, an isolation structure, a gate dielectric layer, a gate, a source region and a drain region. The semiconductor substrate has a plurality of grooves extending downward from a surface of the semiconductor substrate to form a sawtooth sectional profile. The isolation structure is disposed on the outside of the plurality of grooves, and extends from the surface downwards into the semiconductor substrate to define a high-voltage area. The gate dielectric layer is disposed on the high-voltage area and partially filled in the plurality of grooves. The gate is disposed on the gate dielectric layer. The source region and the drain region are respectively disposed in the semiconductor substrate and isolated from each other.
    Type: Application
    Filed: September 13, 2022
    Publication date: January 5, 2023
    Inventors: Sheng-Yao HUANG, Yu-Ruei CHEN, Zen-Jay TSAI, Yu-Hsiang LIN
  • Patent number: 11545463
    Abstract: A method for forming a chip package structure is provided. The method includes forming a first conductive bump and a first ring-like structure over a chip. The first ring-like structure surrounds the first conductive bump, the first ring-like structure and the first conductive bump are made of a same first material, the chip includes an interconnect structure, and the first ring-like structure is electrically insulated from the interconnect structure and the first conductive bump. The method includes bonding the chip to a substrate through the first conductive bump.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: January 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sheng-Yao Yang, Ling-Wei Li, Yu-Jui Wu, Cheng-Lin Huang, Chien-Chen Li, Lieh-Chuan Chen, Che-Jung Chu, Kuo-Chio Liu