Sheng YU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: An electrode plate includes a metal foil, a first active material layer directly disposed on the top surface of the metal foil, and a second active material layer directly disposed on the bottom surface of the metal foil. The crystalline system of the first active material layer is different from that of the second active material layer.
Abstract: A vacuum lamination system includes a film supply assembly, a film collection assembly, a lower lamination body, an upper lamination body, an air extractor, a moving assembly and a cutting assembly. The lower lamination body includes a first casing base and a lower heating assembly vertically movable and disposed in the first casing base. The lower heating assembly carries and moves the substrate so that the substrate is substantially flush with a top surface of the first casing base or retracted into the first casing base. The upper lamination body is vertically movable and disposed above the lower lamination body and includes an upper casing and an upper heating assembly disposed on the upper casing. The air extractor is connected to the lower lamination body. The moving assembly changes a height of a portion of the film. The cutting assembly cuts a portion of the film laminated onto the substrate.
Abstract: A probe head includes upper and lower die units, and a linear probe inserted therethrough and thereby defined with tail, body and head portions. A first bottom surface of the upper die unit and a second top surface of the lower die unit face each other, thereby defining an inner space wherein the body portion is located and includes a plurality of sections each having front width larger than or equal to back width, including a narrowest section whose upper and lower ends have a distance from the first bottom surface and the second top surface respectively. The head and tail portions are offset from each other along two horizontal axes and the body portion is thereby curved. The present invention is favorable in dynamic behavior control of the linear probe which is easy in manufacturing, lower in cost and has more variety in material.
Abstract: This application provides a packet sending method, applied to a communications system including at least two nodes, the at least two nodes include at least one parent node having a child node, a packet sent by the child node is forwarded by the parent node, and the method includes: receiving, by a first node, first instruction information, where the first instruction information is used to instruct the first node to send a packet after a first moment, and the first node is a parent node; and sending, by the first node, a first packet according to the first instruction information.
Abstract: An efficient electronic structure for circuit design, testing and/or manufacture for validating a cell layout design using an intelligent engine trained using selectively arranged cells selected from a cell library. An initial design rule violation (DRV) prediction engine is initially trained using a plurality of pin patterns generated by predefined cell placement combinations, where pin patterns are pixelized and quantified and is classified as either (i) a DRV pin pattern (i.e., pin patterns likely to produce a DRV) or (ii) a DRV-clean pin pattern (i.e., pin patterns unlikely to produce a DRV).
May 15, 2020
Date of Patent:
November 30, 2021
Tao-Chun Yu, Hsien-Shih Chiu, Shao-Yun Fang, Kai-Shun Hu, Philip Hui-Yuh Tai, Cindy Chin-Fang Shen, Henry Sheng
Abstract: A method includes forming a first dummy gate and a second dummy gate over a fin that protrudes above a substrate; replacing the first dummy gate and the second dummy gate with a first metal gate and a second metal gate, respectively; forming a dielectric cut pattern between the first and the second metal gates, the dielectric cut pattern extending further from the substrate than the first and the second metal gates; forming a patterned mask layer over the first metal gate, the second metal gate, and the dielectric cut pattern, an opening in the patterned mask layer exposing a portion of the first metal gate, a portion of the second metal gate, and a portion of the dielectric cut pattern underlying the opening; filling the opening with a first electrically conductive material; and recessing the first electrically conductive material below an upper surface of the dielectric cut pattern.
Yan Chen, Debra Gardner, David M. Knight, Michael W. Lark, Bailin Liang, David M. Marquis, David J. Shealy, Eric Michael Smith, Xiao-yu R. Song, Vedrana Stojanovic-Susulic, Raymond Sweet, Susan Tam, Alain P. Vasserot, Sheng-Jiun Wu, Jing Yang
Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of lower interconnect layers disposed within a lower dielectric structure over a substrate. A lower insulating structure is over the lower dielectric structure and has sidewalls extending through the lower insulating structure. A bottom electrode is arranged along the sidewalls and an upper surface of the lower insulating structure. The upper surface of the lower insulating structure extends past outermost sidewalls of the bottom electrode. A data storage structure is disposed on the bottom electrode and is configured to store a data state. A top electrode is disposed on the data storage structure. The bottom electrode has interior sidewalls coupled to a horizontally extending surface to define a recess within an upper surface of the bottom electrode. The horizontally extending surface is below the upper surface of the lower insulating structure.
Abstract: A method of forming dice includes the following steps. First, a wafer structure is provides, which includes a substrate and a stack of semiconductor layers disposed in die regions and a scribe line region. Then, the substrate and the stack of the semiconductor layers in the scribe line region are removed to forma groove in the substrate. After the formation of the groove, the substrate is further thinned to obtain the substrate with a reduced thickness. Finally, a separation process is performed on the substrate with the reduced thickness.
Abstract: A semiconductor device comprises a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductive bump over the conductive pad, a conductive cap over the conductive bump, and a passivation layer over the semiconductor substrate and surrounding the conductive bump. A combination of the conductive bump and the conductive cap has a stepped sidewall profile. The passivation layer has an inner sidewall at least partially facing and spaced apart from an outer sidewall of the conductive bump.
Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin over the base. The semiconductor device structure includes a gate stack wrapping around a first upper portion of the fin. The semiconductor device structure includes a first stressor and a second stressor respectively over opposite first sides of the fin. The semiconductor device structure includes a spacer structure between the gate stack and the first stressor. The semiconductor device structure includes a first spacer layer covering a sidewall of the gate stack, the spacer structure, and the first stressor. The semiconductor device structure includes a dielectric layer over the first spacer layer. The semiconductor device structure includes an etch stop layer between the first spacer layer and the dielectric layer. The semiconductor device structure includes a seal structure between the second upper portion and the third upper portion.
Abstract: The present invention performs high-throughput disassembly for executable code comprising a plurality of instructions. An input of the executable code is received. Exhaustive disassembly is performed on the executable code to produce a set of exhaustively disassembled instructions. An instruction flow graph is constructed from the exhaustively disassembled instructions. Instruction embedding is performed on the exhaustively disassembled instructions to construct embeddings.
April 29, 2021
November 11, 2021
DEEPBITS TECHNOLOGY INC., THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
Abstract: A wireless audio output device including a first audio output unit and a second audio output unit is provided. The wireless audio output device establishes a wireless link with an audio source, which outputs a first original audio data and a second original audio data. The first and the second audio output units simultaneously output and play the first and the second original audio data. When the first audio output unit successfully receives the first original audio data but the second audio output unit fails to receive the second original audio data, the first audio output unit drops the received first original audio data, and the first and the second audio output units generate a first concealment audio data and a second concealment audio data, respectively, by using a PLC algorithm and play the first concealment audio data and the second concealment audio data, respectively.
July 10, 2020
Date of Patent:
November 9, 2021
AIROHA TECHNOLOGY CORP.
Sheng-Yu Chiu, Kai-Sheng Chen, Hsi-Yuan Tsai, Chih-Kang Wang
Abstract: A method of forming a semiconductor device includes providing a device having a gate stack including a metal gate layer. The device further includes a spacer layer disposed on a sidewall of the gate stack and a source/drain feature adjacent to the gate stack. The method further includes performing a first etch-back process to the metal gate layer to form an etched-back metal gate layer. In some embodiments, the method includes depositing a metal layer over the etched-back metal gate layer. In some cases, a semiconductor layer is formed over both the metal layer and the spacer layer to provide a T-shaped helmet layer over the gate stack and the spacer layer.
Abstract: The present disclosure discloses a pixel circuit, a method for driving the same, a display panel and a display device. The pixel circuit includes: a first switching transistor, a second switching transistor, a first capacitor, a second capacitor, a driving transistor, and a light emitting device; where a gate electrode of the first switching transistor is connected with a scanning signal end, a first electrode of the first switching transistor is connected with a reference signal end, and a second electrode of the first switching transistor is connected with a gate electrode of the driving transistor; and a gate electrode of the second switching transistor is connected with a light emitting control signal end, a first electrode of the second switching transistor is connected with a first power supply end, and a second electrode of the second switching transistor is connected with a first electrode of the driving transistor.
Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.
Abstract: A gas barrier laminate includes an organic layer and an inorganic layered unit. The organic layer includes a product obtained by subjecting a silane compound having an alkoxy group to hydrolysis and condensation. The inorganic layered unit is disposed on the organic layer, and includes an aluminum oxide layer, a hafnium oxide layer, and a silicon aluminum oxide layer that are laminated to one another.
Abstract: A digital self-injection-locked (SIL) radar includes a digital SIL oscillator, a wireless signal transceiver and a digital frequency demodulator. The digital SIL oscillator generates a digital output signal. The wireless signal transceiver is electrically connected to the digital SIL oscillator to convert the digital output signal into a wireless signal for transmission to a target, receives a reflected signal from the target, and converts the reflected signal into a digital injection signal for injection into the digital SIL oscillator. Accordingly, the digital SIL oscillator operates in an SIL state and generates a digital oscillation signal. The digital frequency demodulator is electrically connected to the digital SIL oscillator to receive and demodulate the digital oscillation signal into a digital demodulation signal.
November 9, 2020
November 4, 2021
Shiang-Hwua Yu, Tzyy-Sheng Horng, Wei-Chih Su
Abstract: A method for generating images with high dynamic range (HDR) based on multiple images captured at different aperture values, under different conditions, or at different shutter speeds is applied in a device. The method inputs the original multiple images into a predetermined model and aligns the multiple images. The method further confirms object images that need to be attended among multiple aligned images and obtains a merge weighting for each of the object images, and merges the images for a generated HDR according to the merge weighting of each image. The device utilizing the method is also disclosed.
Abstract: Some embodiments relate to a ferroelectric random access memory (FeRAM) device. The FeRAM device includes a bottom electrode structure and a top electrode overlying the ferroelectric structure. The top electrode has a first width as measured between outermost sidewalls of the top electrode. A ferroelectric structure separates the bottom electrode structure from the top electrode. The ferroelectric structure has a second width as measured between outermost sidewalls of the ferroelectric structure. The second width is greater than the first width such that the ferroelectric structure includes a ledge that reflects a difference between the first width and the second width. A dielectric sidewall spacer structure is disposed on the ledge and covers the outermost sidewalls of the top electrode.