Patents by Inventor Sheng-Yu Wu

Sheng-Yu Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230032773
    Abstract: A sensing system is disclosed. The sensing system includes a sensor cartridge and a readout device. The sensor cartridge includes a sensing device and a micro-channel-structure. The sensing device includes a chip member and an electrode member arranged projectively offset from each other.
    Type: Application
    Filed: December 23, 2020
    Publication date: February 2, 2023
    Inventors: CHIH-CHEN LIN, CHIA-NAN CHIEN, JUNG-HSIN WU, TSUNG-CHIH HUANG, CHIH-HAO CHU, TIEH-KANG WU, SHENG-YU SHIAO
  • Publication number: 20230024491
    Abstract: A method is provided forming an airtight structure of an electroacoustic device which includes a body shell composed of at least two half-shells and at least one airtight structure region. The method includes providing an automatic glue dispensing device for dispensing and pre-curing a photo-curing glue for one of the two half-shells, putting the half-shell into a photo-curing device to convert the photo-curing glue pre-cured completely into an elastomer, and combining the half-shell and the other one to have a pressing wall of the other half-shell to press the elastomer to form the airtight structure of the electroacoustic device, wherein the automatic glue dispensing device includes a glue dispensing head moving on a groove of the airtight region of the half-shell for dispensing the photo-curing glue and a pre-curing head continuously providing a curing light ray for pre-curing the photo-curing glue.
    Type: Application
    Filed: July 23, 2021
    Publication date: January 26, 2023
    Inventors: Tan-Chih WU, Chia-Yen LI, Hung-Wei CHEN, Yi-Ku HUANG, Chene-Lun LEE, Ting-Yu WANG, Hsuan-Yi LIAO, Sheng-Wei CHEN, Jen-Hsin CHAN
  • Patent number: 11555981
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: January 17, 2023
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Liang-Ting Ho, Chen-Er Hsu, Yi-Liang Chan, Fu-Lai Tseng, Fu-Yuan Wu, Chen-Chi Kuo, Ying-Jen Wang, Wei-Han Hsia, Yi-Hsin Tseng, Wen-Chang Lin, Chun-Chia Liao, Shou-Jen Liu, Chao-Chun Chang, Yi-Chieh Lin, Shang-Yu Hsu, Yu-Huai Liao, Shih-Wei Hung, Sin-Hong Lin, Kun-Shih Lin, Yu-Cheng Lin, Wen-Yen Huang, Wei-Jhe Shen, Chih-Shiang Wu, Sin-Jhong Song, Che-Hsiang Chiu, Sheng-Chang Lin
  • Publication number: 20230007912
    Abstract: A semiconductor package includes a package substrate; semiconductor devices disposed on the package substrate; a package ring disposed on a perimeter of the package substrate surrounding the semiconductor devices; a cover including silicon bonded to the package ring and covering the semiconductor devices; and a thermal interface structure (TIS) thermally connecting the semiconductor devices to the cover.
    Type: Application
    Filed: January 17, 2022
    Publication date: January 12, 2023
    Inventors: Jen Yu WANG, Chung-Jung WU, Sheng-Tsung HSIAO, Tung-Liang SHAO, Chih-Hang TUNG, Chen-Hua YU
  • Publication number: 20220355437
    Abstract: A method includes supplying slurry onto a polishing pad; holding a wafer against the polishing pad with a piezoelectric layer interposed vertically between a pressure unit and the wafer; exerting a force on the piezoelectric layer using the pressure unit to make the piezoelectric layer directly press the wafer; generating, using the piezoelectric layer, a first voltage corresponding to a first portion of the wafer and a second voltage corresponding to a second portion of the wafer; tuning the force exerted on the piezoelectric layer according to the first voltage and the second voltage; and polishing, using the polishing pad, the wafer.
    Type: Application
    Filed: July 22, 2022
    Publication date: November 10, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu-Bin HSU, Ren-Guei LIN, Feng-Inn WU, Sheng-Chen WANG, Jung-Yu LI
  • Patent number: 11493536
    Abstract: A probe head includes upper and lower die units, and a linear probe inserted therethrough and thereby defined with tail, body and head portions. A first bottom surface of the upper die unit and a second top surface of the lower die unit face each other, thereby defining an inner space wherein the body portion is located and includes a plurality of sections each having front width larger than or equal to back width, including a narrowest section whose upper and lower ends have a distance from the first bottom surface and the second top surface respectively. The head and tail portions are offset from each other along two horizontal axes and the body portion is thereby curved. The present invention is favorable in dynamic behavior control of the linear probe which is easy in manufacturing, lower in cost and has more variety in material.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: November 8, 2022
    Assignee: MPI CORPORATION
    Inventors: Tzu-Yang Chen, Chin-Yi Lin, Chen-Rui Wu, Sheng-Yu Lin, Ming-Ta Hsu, Chia-Ju Wei
  • Patent number: 11476772
    Abstract: A voltage converter circuit, comprising: a bridge rectifier; a first transistor, having a first end, a second end and a third end; a second transistor, having a first end and a second end; wherein the first end of the first transistor and the first end of second transistor are electrically connected to bridge rectifier, and the second end of the first transistor is electrically connected to the first end of the second transistor; and a Zener diode, connected between the third end of the first transistor and the second end of the second transistor.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: October 18, 2022
    Assignee: EPISTAR CORPORATION
    Inventors: Sheng-Bo Wang, Chiao Fu, Chang-Hsieh Wu, Jai-Tai Kuo, Chao-Kai Chang, Yao-Zhong Liu, Yi-Ru Shen, Chen-Yu Wang
  • Publication number: 20220310482
    Abstract: Semiconductor devices including lids having liquid-cooled channels and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first integrated circuit die; a lid coupled to the first integrated circuit die, the lid including a plurality of channels in a surface of the lid opposite the first integrated circuit die; a cooling cover coupled to the lid opposite the first integrated circuit die; and a heat transfer unit coupled to the cooling cover through a pipe fitting, the heat transfer unit being configured to supply a liquid coolant to the plurality of channels through the cooling cover.
    Type: Application
    Filed: June 15, 2022
    Publication date: September 29, 2022
    Inventors: Sheng-Tsung Hsiao, Jen Yu Wang, Chung-Jung Wu, Tung-Liang Shao, Chih-Hang Tung
  • Publication number: 20220262705
    Abstract: A semiconductor device includes a package and a cooling cover. The package includes a first die having an active surface and a rear surface opposite to the active surface. The rear surface has a cooling region and a peripheral region enclosing the cooling region. The first die includes micro-trenches located in the cooling region of the rear surface. The cooling cover is stacked on the first die. The cooling cover includes a fluid inlet port and a fluid outlet port located over the cooling region and communicated with the micro-trenches.
    Type: Application
    Filed: April 28, 2022
    Publication date: August 18, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Jung Wu, Chih-Hang Tung, Tung-Liang Shao, Sheng-Tsung Hsiao, Jen-Yu Wang
  • Patent number: 11410910
    Abstract: Semiconductor devices including lids having liquid-cooled channels and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first integrated circuit die; a lid coupled to the first integrated circuit die, the lid including a plurality of channels in a surface of the lid opposite the first integrated circuit die; a cooling cover coupled to the lid opposite the first integrated circuit die; and a heat transfer unit coupled to the cooling cover through a pipe fitting, the heat transfer unit being configured to supply a liquid coolant to the plurality of channels through the cooling cover.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Tsung Hsiao, Jen Yu Wang, Chung-Jung Wu, Tung-Liang Shao, Chih-Hang Tung
  • Patent number: 11407083
    Abstract: A method includes supplying slurry onto a polishing pad. A wafer is held against the polishing pad with a first piezoelectric layer interposed between a pressure unit and the wafer. A first voltage generated by the first piezoelectric layer is detected. The wafer is pressed, using the pressure unit, against the polishing pad according to the detected first voltage generated by the first piezoelectric layer. The wafer is polished using the polishing pad.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu-Bin Hsu, Ren-Guei Lin, Feng-Inn Wu, Sheng-Chen Wang, Jung-Yu Li
  • Patent number: 11387164
    Abstract: A semiconductor device includes a package and a cooling cover. The package includes a first die having an active surface and a rear surface opposite to the active surface. The rear surface has a cooling region and a peripheral region enclosing the cooling region. The first die includes micro-trenches located in the cooling region of the rear surface. The cooling cover is stacked on the first die. The cooling cover includes a fluid inlet port and a fluid outlet port located over the cooling region and communicated with the micro-trenches.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: July 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Jung Wu, Chih-Hang Tung, Tung-Liang Shao, Sheng-Tsung Hsiao, Jen-Yu Wang
  • Publication number: 20220149141
    Abstract: A display device includes a semiconductor substrate, an isolation layer, a light-emitting layer and a second electrode. The semiconductor substrate has a pixel region and a peripheral region located around the pixel region. The semiconductor substrate includes first electrodes and a driving element layer. The first electrodes are disposed in the pixel region and the first electrodes are electrically connected to the driving element layer. The isolation layer is disposed on the semiconductor substrate. The isolation layer includes a first isolation pattern disposed in the peripheral region, and the first isolation pattern has a first side surface and a second side surface opposite to the first side surface. The light-emitting layer is disposed on the isolation layer and the first electrodes, and covers the first side surface and the second side surface of the first isolation pattern. The second electrode is disposed on the light-emitting layer.
    Type: Application
    Filed: January 21, 2022
    Publication date: May 12, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Yu Wu, Mirng-Ji Lii, Shang-Yun Tu, Ching-Hui Chen
  • Patent number: 11315896
    Abstract: A pillar structure, and a method of forming, for a substrate is provided. The pillar structure may have one or more tiers, where each tier may have a conical shape or a spherical shape. In an embodiment, the pillar structure is used in a bump-on-trace (BOT) configuration. The pillar structures may have circular shape or an elongated shape in a plan view. The substrate may be coupled to another substrate. In an embodiment, the another substrate may have raised conductive traces onto which the pillar structure may be coupled.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: April 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tin-Hao Kuo, Chen-Shien Chen, Mirng-Ji Lii, Chen-Hua Yu, Sheng-Yu Wu, Yao-Chun Chuang
  • Publication number: 20220077094
    Abstract: A semiconductor device includes a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductive bump, a conductive cap over the conductive bump, and a passivation layer. The conductive pad is over the semiconductor substrate. The conductive bump is over the conductive pad, wherein the conductive bump has a stepped sidewall structure including a lower sidewall, an upper sidewall laterally offset from the lower sidewall, and an intermediary surface laterally extending from a bottom edge of the upper sidewall to a top edge of the lower sidewall. The conductive cap is over the conductive bump. The passivation layer is over the semiconductor substrate and laterally surrounds the conductive bump, wherein the passivation layer has a top surface higher than the intermediary surface of the stepped sidewall structure of the conductive bump and lower than a top surface of conductive cap.
    Type: Application
    Filed: November 12, 2021
    Publication date: March 10, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Yu WU, Ching-Hui CHEN, Mirng-Ji LII, Kai-Di WU, Chien-Hung KUO, Chao-Yi WANG, Hon-Lin HUANG, Zi-Zhong WANG, Chun-Mao CHIU
  • Patent number: 11239305
    Abstract: A display device includes a semiconductor substrate, an isolation layer, a light-emitting layer and a second electrode. The semiconductor substrate has a pixel region and a peripheral region located around the pixel region. The semiconductor substrate includes first electrodes and a driving element layer. The first electrodes are disposed in the pixel region and the first electrodes are electrically connected to the driving element layer. The isolation layer is disposed on the semiconductor substrate. The isolation layer includes a first isolation pattern disposed in the peripheral region, and the first isolation pattern has a first side surface and a second side surface opposite to the first side surface. The light-emitting layer is disposed on the isolation layer and the first electrodes, and covers the first side surface and the second side surface of the first isolation pattern. The second electrode is disposed on the light-emitting layer.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: February 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Yu Wu, Mirng-Ji Lii, Shang-Yun Tu, Ching-Hui Chen
  • Patent number: 11177228
    Abstract: A semiconductor device comprises a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductive bump over the conductive pad, a conductive cap over the conductive bump, and a passivation layer over the semiconductor substrate and surrounding the conductive bump. A combination of the conductive bump and the conductive cap has a stepped sidewall profile. The passivation layer has an inner sidewall at least partially facing and spaced apart from an outer sidewall of the conductive bump.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: November 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Yu Wu, Ching-Hui Chen, Mirng-Ji Lii, Kai-Di Wu, Chien-Hung Kuo, Chao-Yi Wang, Hon-Lin Huang, Zi-Zhong Wang, Chun-Mao Chiu
  • Patent number: 11152273
    Abstract: Conductive structures and the redistribution circuit structures are disclosed. One of the conductive structures includes a first conductive layer and a second conductive layer. The first conductive layer is disposed in a lower portion of a dielectric layer, and the first conductive layer includes an upper surface with a protrusion at an edge. The second conductive layer is disposed in an upper portion of the dielectric layer and electrically connected to the first conductive layer. An upper surface of the second conductive layer is conformal with the upper surface of the first conductive layer.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shang-Yun Tu, Ching-Wen Hsiao, Sheng-Yu Wu, Ching-Hui Chen
  • Publication number: 20210313287
    Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.
    Type: Application
    Filed: June 21, 2021
    Publication date: October 7, 2021
    Inventors: Yu-Wei Lin, Sheng-Yu Wu, Yu-Jen Tseng, Tin-Hao Kuo, Chen-Shien Chen
  • Patent number: 11043462
    Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: June 22, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yu-Wei Lin, Sheng-Yu Wu, Yu-Jen Tseng, Tin-Hao Kuo, Chen-Shien Chen