Patents by Inventor Sheng-Yu Wu

Sheng-Yu Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200243410
    Abstract: Conductive structures and the redistribution circuit structures are disclosed. One of the conductive structures includes a first conductive layer and a second conductive layer. The first conductive layer is disposed in a lower portion of a dielectric layer, and the first conductive layer includes an upper surface with a protrusion at an edge. The second conductive layer is disposed in an upper portion of the dielectric layer and electrically connected to the first conductive layer. An upper surface of the second conductive layer is conformal with the upper surface of the first conductive layer.
    Type: Application
    Filed: April 20, 2020
    Publication date: July 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Yun Tu, Ching-Wen Hsiao, Sheng-Yu Wu, Ching-Hui Chen
  • Publication number: 20200126939
    Abstract: A package includes a first and a second package component. The first package component includes a first metal trace and a second metal trace at the surface of the first package component. The second metal trace is parallel to the first metal trace. The second metal trace includes a narrow metal trace portion having a first width, and a wide metal trace portion having a second width greater than the first width connected to the narrow metal trace portion. The second package component is over the first package component. The second package component includes a metal bump overlapping a portion of the first metal trace, and a conductive connection bonding the metal bump to the first metal trace. The conductive connection contacts a top surface and sidewalls of the first metal trace. The metal bump is neighboring the narrow metal trace portion.
    Type: Application
    Filed: December 20, 2019
    Publication date: April 23, 2020
    Inventors: Sheng-Yu Wu, Tin-Hao Kuo, Chen-Shien Chen
  • Patent number: 10629509
    Abstract: Redistribution circuit structures and methods of forming the same are disclosed. One of the redistribution circuit structures includes a first conductive structure, a dielectric layer and a second conductive structure. The dielectric layer is disposed over and exposes a portion of the first conductive structure. The second conductive structure is disposed in the dielectric layer to electrically connect to the first conductive structure, and includes a first conductive layer and a second conductive layer disposed on and electrically connected to the first conductive layer. The first conductive layer includes a main portion and a conductive protrusion, the conductive protrusion is disposed on an entire edge of an upper surface of the main portion, and a top of the conductive protrusion is higher than the upper surface of the main portion.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Yun Tu, Ching-Wen Hsiao, Sheng-Yu Wu, Ching-Hui Chen
  • Publication number: 20200058601
    Abstract: A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 ?m. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 ?m. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 ?m. In another embodiment the underbump metallization has a first dimension that is less than a dimension of the contact pad and a second dimension that is greater than a dimension of the contact pad.
    Type: Application
    Filed: October 23, 2019
    Publication date: February 20, 2020
    Inventors: Yu-Feng Chen, Yen-Liang Lin, Tin-Hao Kuo, Sheng-Yu Wu, Chen-Shien Chen
  • Patent number: 10515919
    Abstract: A package includes a first and a second package component. The first package component includes a first metal trace and a second metal trace at the surface of the first package component. The second metal trace is parallel to the first metal trace. The second metal trace includes a narrow metal trace portion having a first width, and a wide metal trace portion having a second width greater than the first width connected to the narrow metal trace portion. The second package component is over the first package component. The second package component includes a metal bump overlapping a portion of the first metal trace, and a conductive connection bonding the metal bump to the first metal trace. The conductive connection contacts a top surface and sidewalls of the first metal trace. The metal bump is neighboring the narrow metal trace portion.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Yu Wu, Tin-Hao Kuo, Chen-Shien Chen
  • Patent number: 10504856
    Abstract: A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 ?m. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 ?m. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 ?m. In another embodiment the underbump metallization has a first dimension that is less than a dimension of the contact pad and a second dimension that is greater than a dimension of the contact pad.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Feng Chen, Yen-Liang Lin, Tin-Hao Kuo, Sheng-Yu Wu, Chen-Shien Chen
  • Publication number: 20190295977
    Abstract: A semiconductor device comprises a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductive bump over the conductive pad, a conductive cap over the conductive bump, and a passivation layer over the semiconductor substrate and surrounding the conductive bump. A combination of the conductive bump and the conductive cap has a stepped sidewall profile. The passivation layer has an inner sidewall at least partially facing and spaced apart from an outer sidewall of the conductive bump.
    Type: Application
    Filed: June 10, 2019
    Publication date: September 26, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Yu WU, Ching-Hui CHEN, Mirng-Ji LII, Kai-Di WU, Chien-Hung KUO, Chao-Yi WANG, Hon-Lin HUANG, Zi-Zhong WANG, Chun-Mao CHIU
  • Publication number: 20190295971
    Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.
    Type: Application
    Filed: June 10, 2019
    Publication date: September 26, 2019
    Inventors: Yu-Wei Lin, Sheng-Yu Wu, Yu-Jen Tseng, Tin-Hao Kuo, Chen-Shien Chen
  • Publication number: 20190279953
    Abstract: Connector structures and methods of forming the same are provided. A method includes forming a first patterned passivation layer on a workpiece, the first patterned passivation layer having a first opening exposing a conductive feature of the workpiece. A seed layer is formed over the first patterned passivation layer and in the first opening. A patterned mask layer is formed over the seed layer, the patterned mask layer having a second opening exposing the seed layer, the second opening overlapping with the first opening. A connector is formed in the second opening. The patterned mask layer is partially removed, an unremoved portion of the patterned mask layer remaining in the first opening. The seed layer is patterned using the unremoved portion of the patterned mask layer as a mask.
    Type: Application
    Filed: May 17, 2019
    Publication date: September 12, 2019
    Inventors: Chen-Shien Chen, Sheng-Yu Wu, Mirng-Ji Lii, Chita Chuang
  • Publication number: 20190259724
    Abstract: A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer.
    Type: Application
    Filed: May 1, 2019
    Publication date: August 22, 2019
    Inventors: Sheng-Yu Wu, Tin-Hao Kuo, Chita Chuang, Chen-Shien Chen
  • Patent number: 10388620
    Abstract: Connector structures and methods of forming the same are provided. A method includes forming a first patterned passivation layer on a workpiece, the first patterned passivation layer having a first opening exposing a conductive feature of the workpiece. A seed layer is formed over the first patterned passivation layer and in the first opening. A patterned mask layer is formed over the seed layer, the patterned mask layer having a second opening exposing the seed layer, the second opening overlapping with the first opening. A connector is formed in the second opening. The patterned mask layer is partially removed, an unremoved portion of the patterned mask layer remaining in the first opening. The seed layer is patterned using the unremoved portion of the patterned mask layer as a mask.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: August 20, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Shien Chen, Sheng-Yu Wu, Mirng-Ji Lii, Chita Chuang
  • Patent number: 10319691
    Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: June 11, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yu-Wei Lin, Sheng-Yu Wu, Yu-Jen Tseng, Tin-Hao Kuo, Chen-Shien Chen
  • Patent number: 10319695
    Abstract: A semiconductor device includes a semiconductor substrate. A pad region is disposed on the semiconductor substrate. A micro bump is disposed on the pad region. The micro bump has a first portion on the pad region and a second portion on the first portion. The first portion and the second portion have different widths. The first portion has a first width and the second portion has a second width. The first width is larger or smaller than the second width. The micro bump includes nickel and gold. The semiconductor device also includes a passivation layer overlying a portion of the pad region.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: June 11, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Yu Wu, Ching-Hui Chen, Mirng-Ji Lii, Kai-Di Wu, Chien-Hung Kuo, Chao-Yi Wang, Hon-Lin Huang, Zi-Zhong Wang, Chun-Mao Chiu
  • Patent number: 10290600
    Abstract: A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Yu Wu, Tin-Hao Kuo, Chita Chuang, Chen-Shien Chen
  • Publication number: 20190131200
    Abstract: Semiconductor packages and methods of forming the same are disclosed. The semiconductor package includes a plurality of chips, a first molding compound, a first redistribution structure, a second molding compound and a second redistribution structure. The first molding compound encapsulates the chips. The first redistribution structure is disposed over the plurality of chips and the first molding compound. The second molding compound surrounds the first molding compound. The second redistribution structure is disposed over the first redistribution structure, the first molding compound and the second molding compound.
    Type: Application
    Filed: January 22, 2018
    Publication date: May 2, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Yun Tu, Ching-Wen Hsiao, Sheng-Yu Wu, Ching-Hui Chen
  • Publication number: 20190006303
    Abstract: A semiconductor device includes a semiconductor substrate. A pad region is disposed on the semiconductor substrate. A micro bump is disposed on the pad region. The micro bump has a first portion on the pad region and a second portion on the first portion. The first portion and the second portion have different widths. The first portion has a first width and the second portion has a second width. The first width is larger or smaller than the second width. The micro bump includes nickel and gold. The semiconductor device also includes a passivation layer overlying a portion of the pad region.
    Type: Application
    Filed: September 26, 2017
    Publication date: January 3, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Yu WU, Ching-Hui CHEN, Mirng-Ji LII, Kai-Di WU, Chien-Hung KUO, Chao-Yi WANG, Hon-Lin HUANG, Zi-Zhong WANG, Chun-Mao CHIU
  • Patent number: 10163844
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate including a plurality of conductive traces and a recess filled with a conductive material electrically coupled to at least one of the plurality of conductive traces. The semiconductor structure also includes semiconductor chip. The semiconductor chip includes a plurality of conductive pads correspondingly electrically connected with the plurality of conductive traces through a plurality of conductive bumps. A height of each of the plurality of conductive bumps is determined by a minimum distance between the plurality of conductive pads and the corresponding conductive traces thereof.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yen-Liang Lin, Tin-Hao Kuo, Sheng-Yu Wu, Chen-Shien Chen
  • Patent number: 10163842
    Abstract: A semiconductor structure includes an interconnect structure, at least one first metal pad, at least one second metal pad, at least one first bump, at least one second bump, at least one photosensitive material, and a bonding layer. The first metal pad and the second metal pad are disposed on and electrically connected to the interconnect structure. The first bump is disposed on the first metal pad. The second bump is disposed on the second metal pad. The photosensitive material is disposed on the first bump. The bonding layer is in contact with the photosensitive material and the second bump. The photosensitive material is disposed between the first bump and the bonding layer.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Hung Kuo, Chin-Yu Ku, Yuh-Sen Chang, Hon-Lin Huang, Sheng-Yu Wu, Ching-Hui Chen, Mirng-Ji Lii
  • Patent number: 10157874
    Abstract: A package component includes a dielectric layer and a metal pad over the dielectric layer. A plurality of openings is disposed in the metal pad. The first plurality of openings is separated from each other by portions of the metal pad, with the portions of the metal pad interconnected to form a continuous metal region.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Chun Tsai, Yu-Feng Chen, Tin-Hao Kuo, Chen-Shien Chen, Yu-Chih Huang, Sheng-Yu Wu
  • Publication number: 20180358316
    Abstract: A pillar structure, and a method of forming, for a substrate is provided. The pillar structure may have one or more tiers, where each tier may have a conical shape or a spherical shape. In an embodiment, the pillar structure is used in a bump-on-trace (BOT) configuration. The pillar structures may have circular shape or an elongated shape in a plan view. The substrate may be coupled to another substrate. In an embodiment, the another substrate may have raised conductive traces onto which the pillar structure may be coupled.
    Type: Application
    Filed: August 20, 2018
    Publication date: December 13, 2018
    Inventors: Tin-Hao Kuo, Chen-Shien Chen, Mirng-Ji Lii, Chen-Hua Yu, Sheng-Yu Wu, Yao-Chun Chuang