Patents by Inventor Sheng-Yu Wu
Sheng-Yu Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150004751Abstract: A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer.Type: ApplicationFiled: September 19, 2014Publication date: January 1, 2015Inventors: Sheng-Yu Wu, Tin-Hao Kuo, Chita Chuang, Chen-Shien Chen
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Patent number: 8922006Abstract: A device includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. The passivation layer has a first opening overlapping the metal pad, wherein the first opening has a first lateral dimension measured in a direction parallel to a major surface of the substrate. A polymer layer is over the passivation layer and covering the edge portions of the metal pad. The polymer layer has a second opening overlapping the metal pad. The second opening has a second lateral dimension measured in the direction. The first lateral dimension is greater than the second lateral dimension by more than about 7 ?m. A Under-Bump metallurgy (UBM) includes a first portion in the second opening, and a second portion overlying portions of the polymer layer.Type: GrantFiled: July 27, 2012Date of Patent: December 30, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-Liang Lin, Chen-Shien Chen, Tin-Hao Kuo, Sheng-Yu Wu, Tsung-Shu Lin, Chang-Chia Huang
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Patent number: 8912649Abstract: A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer.Type: GrantFiled: August 17, 2011Date of Patent: December 16, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Yu Wu, Tin-Hao Kuo, Chita Chuang, Chen-Shien Chen
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Publication number: 20140346673Abstract: Methods and apparatuses for a attaching a first substrate to a second substrate are provided. In some embodiments, a first substrate has a protective layer, such as a solder mask, around a die attach area, at which a second substrate is attached. A keep-out region (e.g., an area between the second substrate and the protective layer) is a region around the second substrate in which the protective layer is not formed or removed. The keep-out region is sized such that a sufficient gap exists between the second substrate and the protective layer to place an underfill between the first substrate and the second substrate while reducing or preventing voids and while allowing traces in the keep-out region to be covered by the underfill.Type: ApplicationFiled: August 13, 2014Publication date: November 27, 2014Inventors: Yen-Liang Lin, Chang-Chia Huang, Tin-Hao Kuo, Sheng-Yu Wu, Chen-Shien Chen
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Publication number: 20140291838Abstract: A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 ?m. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 ?m. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 ?m. In another embodiment the underbump metallization has a first dimension that is less than a dimension of the contact pad and a second dimension that is greater than a dimension of the contact pad.Type: ApplicationFiled: June 11, 2014Publication date: October 2, 2014Inventors: Yu-Feng Chen, Yen-Liang Lin, Tin-Hao Kuo, Sheng-Yu Wu, Chen-Shien Chen
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Patent number: 8823170Abstract: A structure comprises a substrate comprising a plurality of traces on top of the substrate, a plurality of connectors formed on a top surface of a semiconductor die, wherein the semiconductor die is formed on the substrate and coupled to the substrate through the plurality of connectors and a dummy metal structure formed at a corner of a top surface of the substrate, wherein the dummy metal structure has two discontinuous sections.Type: GrantFiled: December 6, 2012Date of Patent: September 2, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Yu Wu, Pei-Chun Tsai, Chih-Horng Chang, Tin-Hao Kuo, Chen-Shien Chen
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Publication number: 20140186591Abstract: A device is provided. The device may comprise an integrated circuit package. The integrated circuit package may comprise a first layer and a solder mask. The first layer may comprise a top surface wherein the solder mask is disposed on the top surface of the first layer. The solder mask may comprise a vertical edge. The vertical edge may form an angle between the top surface of the first layer and the vertical edge of not less than 90 degrees. The angle may be not less than 120 degrees or not less than 150 degrees.Type: ApplicationFiled: January 3, 2013Publication date: July 3, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Horng Chang, Sheng-Yu Wu, Pei-Chun Tsai, Tin-Hao Kuo, Chen-Shien Chen
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Publication number: 20140159232Abstract: A structure comprises a substrate comprising a plurality of traces on top of the substrate, a plurality of connectors formed on a top surface of a semiconductor die, wherein the semiconductor die is formed on the substrate and coupled to the substrate through the plurality of connectors and a dummy metal structure formed at a corner of a top surface of the substrate, wherein the dummy metal structure has two discontinuous sections.Type: ApplicationFiled: December 6, 2012Publication date: June 12, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sheng-Yu Wu, Pei-Chun Tsai, Chih-Horng Chang, Tin-Hao Kuo, Chen-Shien Chen
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Publication number: 20140131865Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes an interconnect structure formed on a substrate; a landing metal trace formed on the interconnect structure and coupled to the interconnect structure, wherein the landing metal trace includes a first width T defined in a first direction; and a metal bump post formed on and aligned with the landing metal trace, wherein the metal bump post includes a second width U defined in the first direction, and the second width U is greater than the first width T.Type: ApplicationFiled: January 30, 2014Publication date: May 15, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hua Yu, Tin-Hao Kuo, Chen-Shien Chen, Mirng-Ji Lii, Sheng-Yu Wu, Yen-Liang Lin
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Patent number: 8664041Abstract: A method and device for preventing the bridging of adjacent metal traces in a bump-on-trace structure. An embodiment comprises determining the coefficient of thermal expansion (CTE) and process parameters of the package components. The design parameters are then analyzed and the design parameters may be modified based on the CTE and process parameters of the package components.Type: GrantFiled: April 12, 2012Date of Patent: March 4, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Jen Tseng, Guan-Yu Chen, Sheng-Yu Wu, Chen-Hua Yu, Mirng-Ji Lii, Chen-Shien Chen, Tin-Hao Kuo
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Patent number: 8643196Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes an interconnect structure formed on a substrate; a landing metal trace formed on the interconnect structure and coupled to the interconnect structure, wherein the landing metal trace includes a first width T defined in a first direction; and a metal bump post formed on and aligned with the landing metal trace, wherein the metal bump post includes a second width U defined in the first direction, and the second width U is greater than the first width T.Type: GrantFiled: March 21, 2012Date of Patent: February 4, 2014Assignee: Taiwan Semiconductor manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Tin-Hao Kuo, Chen-Shien Chen, Mirng-Ji Lii, Sheng-Yu Wu, Yen-Liang Lin
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Patent number: 8623756Abstract: A system and method for forming conductive connections is disclosed. An embodiment comprises forming conductive material on to contacts of a semiconductor substrate. The semiconductor substrate is then inverter such that the conductive material is beneath the semiconductor substrate, and the conductive material is reflowed to form a conductive bump. The reflow is performed using gravity in order to form a more uniform shape for the conductive bump.Type: GrantFiled: June 23, 2011Date of Patent: January 7, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chita Chuang, Sheng-Yu Wu, Tin-Hao Kuo, Pei-Chun Tsai, Ming-Da Cheng, Chen-Shien Chen
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Patent number: 8598691Abstract: Semiconductor devices and methods of manufacturing and packaging thereof are disclosed. In one embodiment, a semiconductor device includes an integrated circuit and a plurality of copper pillars coupled to a surface of the integrated circuit. The plurality of copper pillars has an elongated shape. At least 50% of the plurality of copper pillars is arranged in a substantially centripetal orientation.Type: GrantFiled: September 9, 2011Date of Patent: December 3, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Yu Wu, Tin-Hao Kuo, Chen-Shien Chen, Ming-Da Cheng
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Publication number: 20130270699Abstract: A pillar structure for a substrate is provided. The pillar structure may have one or more tiers, where each tier may have a conical shape or a spherical shape. In an embodiment, the pillar structure is used in a bump-on-trace (BOT) configuration. The pillar structures may have circular shape or an elongated shape in a plan view. The substrate may be coupled to another substrate. In an embodiment, the another substrate may have raised conductive traces onto which the pillar structure may be coupled.Type: ApplicationFiled: April 17, 2012Publication date: October 17, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tin-Hao Kuo, Chen-Shien Chen, Mirng-Ji Lii, Chen-Hua Yu, Sheng-Yu Wu, Yao-Chun Chuang
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Publication number: 20130270693Abstract: A method and device for preventing the bridging of adjacent metal traces in a bump-on-trace structure. An embodiment comprises determining the coefficient of thermal expansion (CTE) and process parameters of the package components. The design parameters are then analyzed and the design parameters may be modified based on the CTE and process parameters of the package components.Type: ApplicationFiled: April 12, 2012Publication date: October 17, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Jen Tseng, Guan-Yu Chen, Sheng-Yu Wu, Chen-Hua Yu, Mirng-Ji Lii, Chen-Shien Chen, Tin-Hao Kuo
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Publication number: 20130256874Abstract: A device includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. The passivation layer has a first opening overlapping the metal pad, wherein the first opening has a first lateral dimension measured in a direction parallel to a major surface of the substrate. A polymer layer is over the passivation layer and covering the edge portions of the metal pad. The polymer layer has a second opening overlapping the metal pad. The second opening has a second lateral dimension measured in the direction. The first lateral dimension is greater than the second lateral dimension by more than about 7 ?m. A Under-Bump metallurgy (UBM) includes a first portion in the second opening, and a second portion overlying portions of the polymer layer.Type: ApplicationFiled: July 27, 2012Publication date: October 3, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Liang Lin, Chen-Shien Chen, Tin-Hao Kuo, Sheng-Yu Wu, Tsung-Shu Lin, Chang-Chia Huang
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Patent number: 8510635Abstract: A method for evaluating failure rate, which is applied to a plurality of semiconductor chips with error checking and correcting function includes the following steps. A first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of first failure bit counting values. The error checking and correcting function of each of the semiconductor chips is off. An aging test is applied to the semiconductor chips. A second read-write test operation as the first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of second failure bit counting values. The number of the semiconductor chips, the first failure bit counting values, the second failure bit counting values and an error checking and correcting coefficient are calculated to obtain a failure rate of the semiconductor chips.Type: GrantFiled: December 28, 2010Date of Patent: August 13, 2013Assignee: United Microelectronics Corp.Inventors: Yun-Chi Yang, Yen-Song Liu, Chin-Hsien Chen, Sheng-Yu Wu, Kuan-Cheng Su
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Publication number: 20130062741Abstract: Semiconductor devices and methods of manufacturing and packaging thereof are disclosed. In one embodiment, a semiconductor device includes an integrated circuit and a plurality of copper pillars coupled to a surface of the integrated circuit. The plurality of copper pillars has an elongated shape. At least 50% of the plurality of copper pillars is arranged in a substantially centripetal orientation.Type: ApplicationFiled: September 9, 2011Publication date: March 14, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Yu Wu, Tin-Hao Kuo, Chen-Shien Chen, Ming-Da Cheng
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Publication number: 20130043583Abstract: A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer.Type: ApplicationFiled: August 17, 2011Publication date: February 21, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Yu Wu, Tin-Hao Kuo, Chita Chuang, Chen-Shien Chen
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Publication number: 20130026614Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes an interconnect structure formed on a substrate; a landing metal trace formed on the interconnect structure and coupled to the interconnect structure, wherein the landing metal trace includes a first width T defined in a first direction; and a metal bump post formed on and aligned with the landing metal trace, wherein the metal bump post includes a second width U defined in the first direction, and the second width U is greater than the first width T.Type: ApplicationFiled: March 21, 2012Publication date: January 31, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Tin-Hao Kuo, Chen-Shien Chen, Mirng-Ji Lii, Sheng-Yu Wu, Yen-Liang Lin