Patents by Inventor Sheng-Yuan Hsueh

Sheng-Yuan Hsueh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130168816
    Abstract: The present invention provides a structure of a resistor comprising: a substrate having an interfacial layer thereon; a resistor trench formed in the interfacial layer; at least a work function metal layer covering the surface of the resistor trench; at least two metal bulks located at two ends of the resistor trench and adjacent to the work function metal layer; and a filler formed between the two metal bulks inside the resistor trench, wherein the metal bulks are direct in contact with the filler.
    Type: Application
    Filed: January 4, 2012
    Publication date: July 4, 2013
    Inventors: Chih-Kai Kang, Sheng-Yuan Hsueh, Shu-Hsuan Chih, Po-Kuang Hsieh, Chia-Chen Sun, Po-Cheng Huang, Shih-Chieh Hsu, Chi-Horn Pai, Yao-Chang Wang, Jie-Ning Yang, Chi-Sheng Tseng, Po-Jui Liao, Kuang-Hung Huang, Shih-Chang Chang
  • Publication number: 20130106448
    Abstract: A test key structure for use in measuring step height includes a substrate, and a pair of test contacts. The substrate includes an isolation region and a diffusion region. The test contact pair includes a first test contact and a second test contact for measuring electrical resistances. The first test contact is disposed on the diffusion region and the second test contact is disposed on the isolation region.
    Type: Application
    Filed: November 1, 2011
    Publication date: May 2, 2013
    Inventors: Chih-Kai Kang, Shu-Hsuan Chih, Sheng-Yuan Hsueh, Chia-Chen Sun, Po-Kuang Hsieh, Chi-Horn Pai, Shih-Chieh Hsu
  • Patent number: 7932104
    Abstract: A method for inspecting a photoresist pattern is disclosed. First, a substrate with a first doping region is provided. Then, a photoresist is formed to cover the substrate. Later, the photoresist is patterned to form a photoresist pattern. Afterwards, the substrate is doped by using the photoresist pattern, and a PN junction exists in the first doping region. Thereafter, a current passing through the PN junction is tested to inspect the photoresist pattern.
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: April 26, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Chia-Chen Sun, Yi-Chung Sheng, Sheng-Yuan Hsueh
  • Publication number: 20110049722
    Abstract: A semiconductor circuit structure includes a substrate and an interconnect structure. The interconnect structure is disposed on the substrate and includes a plurality of circuit patterns and at least one closed loop pattern. The closed loop pattern is in a same layer with the circuit patterns, surrounds between the circuit patterns and is insulated from the circuit patterns. The closed loop pattern can protect the circuit patterns from being damaged by stresses, for improving a mechanical strength of the semiconductor circuit structure.
    Type: Application
    Filed: August 26, 2009
    Publication date: March 3, 2011
    Inventors: Chia-Chen Sun, Shih-Chieh Hsu, Yi-Chung Sheng, Sheng-Yuan Hsueh, Yao-Chang Wang
  • Publication number: 20100297791
    Abstract: A method for inspecting a photoresist pattern is disclosed. First, a substrate with a first doping region is provided. Then, a photoresist is formed to cover the substrate. Later, the photoresist is patterned to form a photoresist pattern. Afterwards, the substrate is doped by using the photoresist pattern, and a PN junction exists in the first doping region. Thereafter, a current passing through the PN junction is tested to inspect the photoresist pattern.
    Type: Application
    Filed: May 19, 2009
    Publication date: November 25, 2010
    Inventors: Chia-Chen Sun, Yi-Chung Sheng, Sheng-Yuan Hsueh
  • Patent number: 7190044
    Abstract: A fuse structure for a semiconductor device is provided. The fuse structure includes a fuse layer between the upper and bottom insulating layers. The fuse layer is connected to the other metal layers through via plugs. The fuse layer includes separate blocks and at least a connecting block and is coupled to at least a heat buffer block of a different layer. Because the heat buffer block is coupled to the blocks of the fuse layer, new fusing point and a new path for effectively dissipating the heat are provided and a longer and sinuous electric current path is obtained between the blocks through the heat buffer blocks. The heat buffer block and the blocks coupled to the heat buffer block can avoid large current flowing through the fuse structure and prevent overheating.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: March 13, 2007
    Assignee: United Microelectronics Corp.
    Inventors: Chun-Wen Cheng, Chia-Wen Liang, Ruey-Chyr Lee, Sheng-Yuan Hsueh
  • Publication number: 20070045772
    Abstract: A fuse structure for a semiconductor device is provided. The fuse structure includes a fuse layer between the upper and bottom insulating layers. The fuse layer is connected to the other metal layers through via plugs. The fuse layer includes separate blocks and at least a connecting block and is coupled to at least a heat buffer block of a different layer. Because the heat buffer block is coupled to the blocks of the fuse layer, new fusing point and a new path for effectively dissipating the heat are provided and a longer and sinuous electric current path is obtained between the blocks through the heat buffer blocks. The heat buffer block and the blocks coupled to the heat buffer block can avoid large current flowing through the fuse structure and prevent overheating.
    Type: Application
    Filed: August 30, 2005
    Publication date: March 1, 2007
    Inventors: Chun-Wen Cheng, Chia-Wen Liang, Ruey-Chyr Lee, Sheng-Yuan Hsueh