Abstract: An array substrate and a manufacturing method therefor, and a display panel are provided. The manufacturing method includes: forming a scan line and a gate on a substrate; forming a first insulating layer covering the scan line and the gate on the substrate; forming a metal oxide semiconductor layer above the first insulating layer, the metal oxide semiconductor layer including a source, a drain and an active layer; coating an upper surface of the metal oxide semiconductor layer with a photosensitive material layer; photoetching the photosensitive material layer from the back side of the substrate by using a first metal layer as a mask to form a channel protection layer; performing conductorization treatment on the metal oxide semiconductor layer to enable the source and the drain to be conductive; forming a data line above the first insulating layer; and forming a pixel electrode above the first insulating layer.

Abstract: A neural network system, comprising: instructions for implementing at least a SWBN layer in a neural network, and wherein the instructions perform operations comprising: during training of the neural network system on a plurality of batches of training data and for each of the plurality of batches: obtaining a respective first layer output for each of the plurality of training data; determining a plurality of normalization statistics for the batch from the first layer outputs; generating a respective normalized output for each training data in the batch; updating the whitening matrix by a covariance matrix; performing stochastic whitening on the normalized components of each first layer output; transforming the whitened data for each training data; generating a respective SWBN layer output for each of the training data from the transformed whitened data for each training data in the batch; and providing the SWBN layer output.

Abstract: An array substrate and a manufacturing method therefor, and a display panel are provided. The manufacturing method includes: forming a scan line and a gate on a substrate; forming a first insulating layer covering the scan line and the gate on the substrate; forming a metal oxide semiconductor layer above the first insulating layer, the metal oxide semiconductor layer including a source, a drain and an active layer; coating an upper surface of the metal oxide semiconductor layer with a photosensitive material layer; photoetching the photosensitive material layer from the back side of the substrate by using a first metal layer as a mask to form a channel protection layer; performing conductorization treatment on the metal oxide semiconductor layer to enable the source and the drain to be conductive; forming a data line above the first insulating layer; and forming a pixel electrode above the first insulating layer.

Abstract: Provided are a method and a device for acquiring a temperature and a computer-readable storage medium. The method for acquiring a temperature includes: building a temperature acquisition model, wherein the temperature acquisition model is configured to acquire, based on an operating parameter of the radioactive substance treatment system input to the temperature acquisition model, a temperature of different parts of the radioactive reactant in the radioactive substance treatment system under a condition of the parameter; inputting a current operating parameter of the radioactive substance treatment system into the temperature acquisition model during the treatment for the radioactive substance; and acquiring a current temperature of different parts of the radioactive reactant in the radioactive substance treatment system output by the temperature acquisition model.

Abstract: Provided are a method and a device for acquiring a temperature and a computer-readable storage medium. The method for acquiring a temperature includes: building a temperature acquisition model, wherein the temperature acquisition model is configured to acquire, based on an operating parameter of the radioactive substance treatment system input to the temperature acquisition model, a temperature of different parts of the radioactive reactant in the radioactive substance treatment system under a condition of the parameter; inputting a current operating parameter of the radioactive substance treatment system into the temperature acquisition model during the treatment for the radioactive substance; and acquiring a current temperature of different parts of the radioactive reactant in the radioactive substance treatment system output by the temperature acquisition model.

Abstract: A neural network system, comprising: instructions for implementing at least a SWBN layer in a neural network, and wherein the instructions perform operations comprising: during training of the neural network system on a plurality of batches of training data and for each of the plurality of batches: obtaining a respective first layer output for each of the plurality of training data; determining a plurality of normalization statistics for the batch from the first layer outputs; generating a respective normalized output for each training data in the batch; updating the whitening matrix by a covariance matrix; performing stochastic whitening on the normalized components of each first layer output; transforming the whitened data for each training data; generating a respective SWBN layer output for each of the training data from the transformed whitened data for each training data in the batch; and providing the SWBN layer output.

Abstract: The present disclosure includes a shift register unit circuit, including input storing module, configured to receive an input signal at an input terminal and store the input signal; storage retrieving module, configured to retrieve the input signal from the input storing module under influence of at least a first clock signal; output driving module, configured to transfer the input signal to an first output terminal under control of the storage retrieving module; and pulling-down and maintaining module, configured to pull down a voltage at the output terminal to low voltage level after output operation is completed, and maintain the voltage at low voltage level until the output driving module receives a next input signal. The present disclosure also includes a gate driver circuit including such shift register units and a method for generating gate driving signal.

Abstract: A gate driving unit and a gate driving method are provided. The gate driving unit includes an input unit, a driving unit, a pull-down unit, and a pull-down control unit. The pull-down unit has an output terminal of a current stage cascaded signal and an output terminal; in the pull-up phase, the output terminal of the current stage cascaded signal and the output terminal output signal, a voltage of the output terminal of the current stage cascaded signal is pulled down to a first reference low electric level, and a voltage of the output terminal is pulled down to a second reference low electric level.

Abstract: The present disclosure includes a shift register unit circuit, including input storing module, configured to receive an input signal at an input terminal and store the input signal; storage retrieving module, configured to retrieve the input signal from the input storing module under influence of at least a first clock signal; output driving module, configured to transfer the input signal to an first output terminal under control of the storage retrieving module; and pulling-down and maintaining module, configured to pull down a voltage at the output terminal to low voltage level after output operation is completed, and maintain the voltage at low voltage level until the output driving module receives a next input signal. The present disclosure also includes a gate driver circuit including such shift register units and a method for generating gate driving signal.

Abstract: A gate driving unit and a gate driving method are provided. The gate driving unit includes an input unit, a driving unit, a pull-down unit, and a pull-down control unit. The pull-down unit has an output terminal of a current stage cascaded signal and an output terminal; in the pull-up phase, the output terminal of the current stage cascaded signal and the output terminal output signal, a voltage of the output terminal of the current stage cascaded signal is pulled down to a first reference low electric level, and a voltage of the output terminal is pulled down to a second reference low electric level.

Abstract: Provided is a pixel circuit. The pixel circuit comprises a driving transistor and a light-emitting element both coupled in series between a first level end and a second level end, and comprises a second transistor, a third transistor, a fourth transistor, a first capacitor and a second capacitor. The second capacitor is coupled between a control electrode of the driving transistor and a second end of the light-emitting element. A threshold voltage is stored by the first capacitor, so that threshold voltage compensation for the driving transistor and the light-emitting element is implemented, and therefore the non-uniformity of the display of the pixel circuit is compensated. Also provided is a display device, wherein a first control line and a light-emitting control line are both global lines. Also disclosed is a pixel circuit driving method.

Abstract: The present application discloses a low-voltage digital to analog conversion circuit, a data driving circuit and a display system. At least one voltage dividing unit comprises a number of resistors connected in series between a lower limit of voltage and an upper limit of voltage, and voltage dividing output terminals drawn from the resistors' connection nodes and an upper limit of voltage connection end. Introducing the voltage dividing unit renders the low-voltage digital signal to analog signal conversion circuit, the data driving circuit, and the display system low-voltage devices with low power consumption and small chip area.

Abstract: An organic light emitting diode panel, a gate driver circuit and a gate driver circuit unit are disclosed, where the gate driver circuit includes a scanning signal generating unit for generating a scanning signal, transmitting a first clock signal to a scanning signal output terminal under the control of a pulse signal, and pulling down and maintaining the voltage of the scanning signal output terminal at a low voltage level under the control of a second clock signal. The gate driver circuit unit also includes a light emitting signal generating unit for generating a light emitting signal, pulling down the voltage of the light emitting signal output terminal under the control of the pulse signal, and charging the light emitting signal output terminal under the control of the second clock signal.

Abstract: The present application provides a gate driver circuit comprising at least one cascaded gate driver circuit unit. The low-level-holding enabling terminal of the gate driver circuit unit is connected to an adaptive voltage generating module. The adaptive voltage generating module generates a self-compensating voltage according to its constant current source and transmits to the low-level-holding enabling terminal, so as to provide an effective voltage level to the low-level-holding enabling terminal. Because the threshold voltage shift caused by pulling-down transistors in the low-level-holding module is embodied at the low-level-holding enabling terminal, the adaptive voltage generating module generates a self-compensating voltage with its constant current source according to the threshold voltage to compensate the increase of the threshold voltage.

Abstract: The present application discloses a shift register and units thereof, wherein low voltage level maintaining module (30) includes: a first maintaining unit (31) and a second maintaining unit (32), configured to maintain a signal output terminal and/or the controlling terminal (Q) of the driving module (20) at low voltage level when an effective level is received. A threshold voltage sensing module (40) is coupled between the first maintaining unit (31) and the second maintaining unit (32), the threshold voltage sensing module (40) is configured to control its signal output terminal to provide an effective level to the second maintain-enabling terminal (P2) according to threshold voltage shift of the first maintaining unit (31) sensed. Therefore, low voltage maintaining module (30) may endure a greater threshold voltage shift, and the life span of the circuit is extended. The present application further discloses a display device and a voltage regulating circuit.

Abstract: A controllable voltage source, comprising a control module (1), a storage module (2) and an output module (3); the control module (1) is coupled between a high level end and a low level end; the storage module (2) comprises a storage capacitor; two ends of the storage capacitor are respectively coupled to the control module (1) to form a first terminal and a second terminal; the output module (3) is coupled to the second terminal, and the signal output end thereof is used to output to an external circuit the voltage signal of the controllable voltage source; the control module (1) responds the effective level of a first clock signal so as to enable the first terminal to be coupled to the high level end, and the first terminal is charged from the high level end; the control module (1) responds the effective level of a second clock signal so as to enable the second terminal to be coupled to the high level end, and the second terminal is charged from the high level end; and the first terminal is coupled to the l

Abstract: A complementary thin film transistor and manufacturing method thereof are provided. The complementary thin film transistor has a substrate, an n-type semiconductor layer, a p-type semiconductor layer, and an etched barrier layer. The substrate defines an n-type transistor region and a p-type transistor region adjacent to the n-type transistor region. The n-type semiconductor layer is disposed on the substrate and within the n-type transistor region, and has a metal oxide material. The p-type semiconductor layer is disposed on the substrate and within the p-type transistor region, and has an organic semiconductor material. The etched barrier layer is formed on the n-type semiconductor layer and disposed within the n-type transistor region and the p-type transistor region, and the p-type semiconductor layer is formed on the etched barrier layer.

Abstract: An organic light emitting diode panel, a gate driver circuit and a gate driver circuit unit are disclosed, where the gate driver circuit includes a scanning signal generating unit for generating a scanning signal, transmitting a first clock signal to a scanning signal output terminal under the control of a pulse signal, and pulling down and maintaining the voltage of the scanning signal output terminal at a low voltage level under the control of a second clock signal. The gate driver circuit unit also includes a light emitting signal generating unit for generating a light emitting signal, pulling down the voltage of the light emitting signal output terminal under the control of the pulse signal, and charging the light emitting signal output terminal under the control of the second clock signal.

Abstract: A shift register is disclosed. The shift register comprises a multistage shift register units. Each of the stage shift register unit comprises: a driving module, charging to the driving signal via the first clock signal based on the driving control signal; an input module, outputting the driving control signal based on the second clock signal and the first control signal; a low level maintenance module, keeping the potential of the driving signal at the low level potential of the second reference. The shift register can avoid the leakage from the first output end, decrease the raising time of the driving signal and occupy the small area.

Abstract: A photoelectric sensor and a display panel comprise: a pulse transmission unit comprising a control node, after obtaining a driving voltage, the control node of the pulse transmission unit transmitting first clock signals to a signal output terminal; a pulse control unit configured to receive scanning signals from a signal input terminal and charging the control node of the pulse transmission unit so as to provide the driving voltage; and photoelectric sensing unit configured to provide a leakage current in response to the intensity of external illumination when receiving the external illumination, the leakage current discharging the control node of the pulse transmission unit, so that the voltage at the control node of the pulse transmission unit is less than the driving voltage after a period of time.