Abstract: A method for fabricating a metal oxide thin film transistor comprises selecting a substrate and fabricating a gate electrode thereon; growing a layer of dielectric or high permittivity dielectric on the substrate to serve as a gate dielectric layer; growing a first metal layer on the gate dielectric layer and a second metal layer on the first metal layer; fabricating a channel region at a middle position of the first metal layer and a passivation region at a middle position of the second metal layer; anodizing the metals of the passivation region and the channel region at atmospheric pressure and room temperature; fabricating a source and a drain; forming an active region comprising the source, the drain, and the channel region; depositing a silicon nitride layer on the active region; fabricating two electrode contact holes; depositing a metal aluminum film; and fabricating two metal contact electrodes by photolithography and etching.

Abstract: An ultraviolet light sensing circuit and sensing system. The ultraviolet light sensing circuit comprises a modulation unit and a phase delay unit, wherein the modulation unit comprises a first stage of inverter which is used for sensing ultraviolet light and is used as a voltage feedback modulation stage; and the phase delay unit comprises N stages of inverters which are connected in sequence, where N is an even number which is greater than or equal to 2. The modulation unit is connected to the phase delay unit in sequence, and the output voltage of the phase delay unit is fed to the modulation unit; and the modulation unit is modulated by a control signal which is a pulse signal. The ultraviolet light sensing circuit and sensing system can be used for ultraviolet light information communications. The ultraviolet light sensing circuit can sense ultraviolet light signals and output amplitude modulation wave signals.

Abstract: A photoelectric sensor and a display panel comprise: a pulse transmission unit comprising a control node, after obtaining a driving voltage, the control node of the pulse transmission unit transmitting first clock signals to a signal output terminal; a pulse control unit configured to receive scanning signals from a signal input terminal and charging the control node of the pulse transmission unit so as to provide the driving voltage; and photoelectric sensing unit configured to provide a leakage current in response to the intensity of external illumination when receiving the external illumination, the leakage current discharging the control node of the pulse transmission unit, so that the voltage at the control node of the pulse transmission unit is less than the driving voltage after a period of time.

Abstract: The present application discloses a shift register and units thereof, wherein low voltage level maintaining module (30) includes: a first maintaining unit (31) and a second maintaining unit (32), configured to maintain a signal output terminal and/or the controlling terminal (Q) of the driving module (20) at low voltage level when an effective level is received. A threshold voltage sensing module (40) is coupled between the first maintaining unit (31) and the second maintaining unit (32), the threshold voltage sensing module (40) is configured to control its signal output terminal to provide an effective level to the second maintain-enabling terminal (P2) according to threshold voltage shift of the first maintaining unit (31) sensed. Therefore, low voltage maintaining module (30) may endure a greater threshold voltage shift, and the life span of the circuit is extended. The present application further discloses a display device and a voltage regulating circuit.

Abstract: A gate driving circuit and a display device are disclosed. The gate driving circuit includes a control module for pulling down the level of the second control node to be at the low level before the gate strobe signals are outputted and during the output period of the gate cutoff signals. In this way, the second pull-down control end of the low level maintaining module is pulled down to be at the low levels, and the low level maintaining module is in the off state. In this way, the electrical leakage of the low level maintaining module may be reduced so as to decrease the output delay of the gate signals and to enhance the efficiency of the circuit.

Abstract: The present application discloses a low-voltage digital to analog conversion circuit, a data driving circuit and a display system. At least one voltage dividing unit comprises a number of resistors connected in series between a lower limit of voltage and an upper limit of voltage, and voltage dividing output terminals drawn from the resistors' connection nodes and an upper limit of voltage connection end. Introducing the voltage dividing unit renders the low-voltage digital signal to analog signal conversion circuit, the data driving circuit, and the display system low-voltage devices with low power consumption and small chip area.

Abstract: The present application provides a gate driver circuit comprising at least one cascaded gate driver circuit unit. The low-level-holding enabling terminal of the gate driver circuit unit is connected to an adaptive voltage generating module. The adaptive voltage generating module generates a self-compensating voltage according to its constant current source and transmits to the low-level-holding enabling terminal, so as to provide an effective voltage level to the low-level-holding enabling terminal. Because the threshold voltage shift caused by pulling-down transistors in the low-level-holding module is embodied at the low-level-holding enabling terminal, the adaptive voltage generating module generates a self-compensating voltage with its constant current source according to the threshold voltage to compensate the increase of the threshold voltage.

Abstract: Provided is a pixel circuit. The pixel circuit comprises a driving transistor and a light-emitting element both coupled in series between a first level end and a second level end, and comprises a second transistor, a third transistor, a fourth transistor, a first capacitor and a second capacitor. The second capacitor is coupled between a control electrode of the driving transistor and a second end of the light-emitting element. A threshold voltage is stored by the first capacitor, so that threshold voltage compensation for the driving transistor and the light-emitting element is implemented, and therefore the non-uniformity of the display of the pixel circuit is compensated. Also provided is a display device, wherein a first control line and a light-emitting control line are both global lines. Also disclosed is a pixel circuit driving method.

Abstract: A complementary thin film transistor and manufacturing method thereof are provided. The complementary thin film transistor has a substrate, an n-type semiconductor layer, a p-type semiconductor layer, a first passivation layer, a first electrode metal layer, and a second electrode metal layer. The n-type semiconductor layer is disposed above the substrate, and comprises a metal oxide material. The p-type semiconductor layer is disposed above the substrate, and comprises an organic semiconductor material. The first passivation layer is disposed between the n-type semiconductor layer and the p-type semiconductor layer, and formed with at least one contacting hole. The first electrode metal layer and the second electrode metal layer are electrically connected with each other through the contacting hole.

Abstract: A complementary thin film transistor and manufacturing method thereof are provided. The complementary thin film transistor has a substrate, an n-type semiconductor layer, a p-type semiconductor layer, a first passivation layer, a first electrode metal layer, and a second electrode metal layer. The n-type semiconductor layer is disposed above the substrate, and comprises a metal oxide material. The p-type semiconductor layer is disposed above the substrate, and comprises an organic semiconductor material. The first passivation layer is disposed between the n-type semiconductor layer and the p-type semiconductor layer, and formed with at least one contacting hole. The first electrode metal layer and the second electrode metal layer are electrically connected with each other through the contacting hole.

Abstract: A complementary thin film transistor and manufacturing method thereof are provided. The complementary thin film transistor has a substrate, an n-type semiconductor layer, and a p-type semiconductor layer. The substrate defines an n-type transistor region and a p-type transistor region adjacent to the n-type transistor region. The n-type semiconductor layer is disposed above the substrate and within the n-type transistor region, and the n-type semiconductor layer comprises a metal oxide material. The p-type semiconductor layer is disposed above the substrate and within the p-type transistor region, and the p-type semiconductor layer comprises an organic semiconductor material.

Abstract: A gate driving circuit and a display device are disclosed. The gate driving circuit includes a control module for pulling down the level of the second control node to be at the low level before the gate strobe signals are outputted and during the output period of the gate cutoff signals. In this way, the second pull-down control end of the low level maintaining module is pulled down to be at the low levels, and the low level maintaining module is in the off state. In this way, the electrical leakage of the low level maintaining module may be reduced so as to decrease the output delay of the gate signals and to enhance the efficiency of the circuit.

Abstract: A method for fabricating a metal oxide thin film transistor comprises the steps of: selecting a substrate and fabricating a gate electrode on the substrate; growing a layer of dielectric or a high permittivity dielectric on the substrate, and allowing the layer of dielectric or high permittivity dielectric to cover the gate electrode to serve as a gate dielectric layer; growing a metal layer on the gate dielectric layer; fabricating a channel in the middle position of the metal layer; anodizing the metal of the channel at atmospheric pressure and room-temperature; fabricating an active region comprising a source, a drain, and the channel; depositing a silicon nitride layer on the active region and forming two contact holes of the electrodes on the silicon nitride layer; and depositing a layer of aluminum film and fabricating two metal contact electrodes of the thin film transistor.

Abstract: A shift register is disclosed. The shift register comprises a multistage shift register units. Each of the stage shift register unit comprises: a driving module, charging to the driving signal via the first clock signal based on the driving control signal; an input module, outputting the driving control signal based on the second clock signal and the first control signal; a low level maintenance module, keeping the potential of the driving signal at the low level potential of the second reference. The shift register can avoid the leakage from the first output end, decrease the raising time of the driving signal and occupy the small area.

Abstract: Disclosed is a CMOS element. The CMOS element comprises a substrate, a first metal layer, an insulation layer and a first type metal oxide semiconductor layer; and the element further comprises a first, a second and a third metal parts which are located on the insulation layer, and the first and the second metal parts are located at two sides of the first type metal oxide semiconductor layer and both contacts therewith; a second type organic semiconductor layer, located in a gap between the second, and the third metal parts and on the second, the third metal parts where are adjacent to the gap; a passivation layer, located on the first, the second and the third metal parts, the first type metal oxide semiconductor layer and the second type organic semiconductor layer; a third metal layer located on the passivation layer corresponding to the second type organic semiconductor layer.

Abstract: An adaptive voltage source, comprising a signal output end, and a reference resistance forming circuit and a sensing module connected in series between a voltage source and a low power level; the sensing module comprises a sensing end coupled to a transistor to be sensed to sense the threshold voltage drift of the transistor to be sensed in a device circuit; the equivalent resistance of the sensing module increases with the increase of the sensed threshold voltage drift; and the signal output end is coupled to a first node coupled to the reference resistance forming circuit and the sensing module, and is used to output adaptive voltage. The output adaptive voltage is adjusted via the threshold voltage drift sensed by the sensing module. Based on the circuit, also disclosed are a shift register and unit thereof, and display.

Abstract: A display device and a pixel circuit thereof. The pixel circuit generates threshold voltage information of a driving transistor (21) in a source following manner, a threshold voltage of the driving transistor (21) and a reference voltage related to gray scale information are generated at two ends of a first capacitor (26) by means of voltage division of the first capacitor (26) and a second capacitor (27), and the reference voltage keeps unchanged during a light-emitting process, so that a driving current flowing through a light-emitting device (25) is irrelevant to threshold voltages of the driving transistor (21) and the light-emitting device (25), thereby compensating the threshold voltage deviation of the driving transistor (21) and the light-emitting device (25), and solving the problem of nonuniform display.

Abstract: A method for fabricating a metal oxide thin film transistor comprises selecting a substrate and fabricating a gate electrode thereon; growing a layer of dielectric or high permittivity dielectric on the substrate to serve as a gate dielectric layer; growing a first metal layer on the gate dielectric layer and a second metal layer on the first metal layer; fabricating a channel region at a middle position of the first metal layer and a passivation region at a middle position of the second metal layer; anodizing the metals of the passivation region and the channel region at atmospheric pressure and room temperature; fabricating a source and a drain; forming an active region comprising the source, the drain, and the channel region; depositing a silicon nitride layer on the active region; fabricating two electrode contact holes; depositing a metal aluminum film; and fabricating two metal contact electrodes by photolithography and etching.

Abstract: A method for fabricating a metal oxide thin film transistor comprises the steps of: selecting a substrate and fabricating a gate electrode on the substrate; growing a layer of dielectric or a high permittivity dielectric on the substrate, and allowing the layer of dielectric or high permittivity dielectric to cover the gate electrode to serve as a gate dielectric layer; growing a metal layer on the gate dielectric layer; fabricating a channel in the middle position of the metal layer; anodizing the metal of the channel at atmospheric pressure and room-temperature; fabricating an active region comprising a source, a drain, and the channel; depositing a silicon nitride layer on the active region and forming two contact holes of the electrodes on the silicon nitride layer; and depositing a layer of aluminum film and fabricating two metal contact electrodes of the thin film transistor.

Abstract: Disclosed is a CMOS element. The CMOS element comprises a substrate, a first metal layer, an insulation layer and a first type metal oxide semiconductor layer; and the element further comprises a first, a second and a third metal parts which are located on the insulation layer, and the first and the second metal parts are located at two sides of the first type metal oxide semiconductor layer and both contacts therewith; a second type organic semiconductor layer, located in a gap between the second, and the third metal parts and on the second, the third metal parts where are adjacent to the gap; a passivation layer, located on the first, the second and the third metal parts, the first type metal oxide semiconductor layer and the second type organic semiconductor layer; a third metal layer located on the passivation layer corresponding to the second type organic semiconductor layer.