Patents by Inventor Shengdong Zhang
Shengdong Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9779662Abstract: A pixel circuit, a drive method based on the pixel circuit, and a display device. The pixel circuit comprises: a first capacitor (C1), a second capacitor (C2), a second transistor (T2), a third transistor (T3) and a light-emitting branch for being coupled between a first common electrode (VDD) and a second common electrode (VSS); wherein the light-emitting branch comprises a first transistor (T1), a fourth transistor (T4) and a light-emitting element (OLED) which are connected in series; a first electrode of the first transistor (T1) is coupled to a second electrode of the fourth transistor (T4), and a coupling node is a third node (C); and a control electrode of the fourth transistor (T4) is used for inputting a second scanning control signal (VEM), and the fourth transistor (T4) switches the ON/OFF state of the light-emitting branch in response to the second scanning control signal (VEM).Type: GrantFiled: November 7, 2014Date of Patent: October 3, 2017Assignee: Peking University Shenzhen Graduate SchoolInventors: Shengdong Zhang, Cuicui Wang, Chuanli Leng, Longyan Wang
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Publication number: 20170270862Abstract: A pixel circuit, a drive method based on the pixel circuit, and a display device. The pixel circuit comprises: a first capacitor (C1), a second capacitor (C2), a second transistor (T2), a third transistor (T3) and a light-emitting branch for being coupled between a first common electrode (VDD) and a second common electrode (VSS); wherein the light-emitting branch comprises a first transistor (T1), a fourth transistor (T4) and a light-emitting element (OLED) which are connected in series; a first electrode of the first transistor (T1) is coupled to a second electrode of the fourth transistor (T4), and a coupling node is a third node (C); and a control electrode of the fourth transistor (T4) is used for inputting a second scanning control signal (VEM), and the fourth transistor (T4) switches the ON/OFF state of the light-emitting branch in response to the second scanning control signal (VEM).Type: ApplicationFiled: November 7, 2014Publication date: September 21, 2017Applicant: PEKING UNIVERSITY SHENZHEN GRADUATE SCHOOLInventors: Shengdong ZHANG, Cuicui WANG, Chuanli LENG, Longyan WANG
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Publication number: 20170213500Abstract: A controllable voltage source, comprising a control module (1), a storage module (2) and an output module (3); the control module (1) is coupled between a high level end and a low level end; the storage module (2) comprises a storage capacitor; two ends of the storage capacitor are respectively coupled to the control module (1) to form a first terminal and a second terminal; the output module (3) is coupled to the second terminal, and the signal output end thereof is used to output to an external circuit the voltage signal of the controllable voltage source; the control module (1) responds the effective level of a first clock signal so as to enable the first terminal to be coupled to the high level end, and the first terminal is charged from the high level end; the control module (1) responds the effective level of a second clock signal so as to enable the second terminal to be coupled to the high level end, and the second terminal is charged from the high level end; and the first terminal is coupled to the lType: ApplicationFiled: November 14, 2014Publication date: July 27, 2017Applicant: PEKING UNIVERSITY SHENZHEN GRADUATE SCHOOLInventors: Shengdong ZHANG, Congwei LIAO, Zhijin HU, Wenjie LI, Junmei LI
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Publication number: 20170097650Abstract: An adaptive voltage source, comprising a signal output end, and a reference resistance forming circuit and a sensing module connected in series between a voltage source and a low power level; the sensing module comprises a sensing end coupled to a transistor to be sensed to sense the threshold voltage drift of the transistor to be sensed in a device circuit; the equivalent resistance of the sensing module increases with the increase of the sensed threshold voltage drift; and the signal output end is coupled to a first node coupled to the reference resistance forming circuit and the sensing module, and is used to output adaptive voltage. The output adaptive voltage is adjusted via the threshold voltage drift sensed by the sensing module. Based on the circuit, also disclosed are a shift register and unit thereof, and display.Type: ApplicationFiled: November 14, 2014Publication date: April 6, 2017Applicant: PEKING UNIVERSITY SHENZHEN GRADUATE SCHOOLInventors: Shengdong ZHANG, Congwei LIAO, Zhijin HU, Wenjie LI, Junmei LI
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Publication number: 20170074722Abstract: An ultraviolet light sensing circuit and sensing system. The ultraviolet light sensing circuit comprises a modulation unit and a phase delay unit, wherein the modulation unit comprises a first stage of inverter which is used for sensing ultraviolet light and is used as a voltage feedback modulation stage; and the phase delay unit comprises N stages of inverters which are connected in sequence, where N is an even number which is greater than or equal to 2. The modulation unit is connected to the phase delay unit in sequence, and the output voltage of the phase delay unit is fed to the modulation unit; and the modulation unit is modulated by a control signal which is a pulse signal. The ultraviolet light sensing circuit and sensing system can be used for ultraviolet light information communications. The ultraviolet light sensing circuit can sense ultraviolet light signals and output amplitude modulation wave signals.Type: ApplicationFiled: November 14, 2014Publication date: March 16, 2017Applicant: PEKING UNIVERSITY SHENZHEN GRADUATE SCHOOLInventors: Shengdong ZHANG, Congwei LIAO, Zhijin HU, Wenjie LI, Junmei LI
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Publication number: 20160043227Abstract: A method of manufacturing a thin film transistor, comprising: forming a gate electrode (2) on a first surface of a substrate (1); forming on the first surface of the substrate a gate dielectric layer (3) covering the gate electrode; forming a metal oxide semiconductor layer (4) on the gate dielectric layer; processing the metal oxide semiconductor layer to form a channel region (5) exposed thereon; anode-oxidizing the channel region, such that the channel region has a first carrier concentration; and conducting photolithography and etching the metal oxide semiconductor layer to form an active region, the active region comprising the channel region, and a source region (6) and a drain region (7) located at the two sides of the channel region and having a second carrier concentration, the first carrier concentration being lower than the second carrier concentration.Type: ApplicationFiled: November 11, 2013Publication date: February 11, 2016Inventors: Shengdong Zhang, Yang Shao, Xin He, Xiang Xiao
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Patent number: 9129992Abstract: Designs and fabrication of dual-gate thin film transistors are provided. An active region and a top gate electrode of the transistor can be made of a transparent thin film material. A photoresist can be coated onto a surface of the transparent conductive thin film for forming the top gate electrode. Light is from the bottom of the substrate during exposure. After the development, a photoresist pattern aligned with the bottom gate electrode is formed on the surface of the conductive thin film. The top gate electrode aligned with the bottom gate electrode is formed by etching the conductive thin film. The bottom gate electrode can be used as a mask, which may save the cost for manufacturing the transistor and improve the accuracy of alignment between the top gate electrode and the bottom gate electrode and the performance of the dual-gate thin film transistor.Type: GrantFiled: June 13, 2011Date of Patent: September 8, 2015Assignee: PEKING UNIVERSITY SHENZHEN GRADUATE SCHOOLInventors: Shengdong Zhang, Xin He, Longyan Wang
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Patent number: 9117418Abstract: The present invention provides a gate driver on array (GOA) circuit and a display panel with the GOA circuit. The driver circuit includes multiple stages of gate driver units and multiple stages of supplementary gate driver units connected in cascade, in which the nth stage gate driver unit includes a driving unit (42) and a pull-down unit (44) and the mth stage supplementary gate driver unit includes a supplementary driving unit (52) and a supplementary pull-down unit (54).Type: GrantFiled: January 24, 2014Date of Patent: August 25, 2015Assignee: Shenzhen China Star Optoelectronics Technology Co., LtdInventors: Shengdong Zhang, Zhijin Hu, Congwei Liao, Limei Zeng, Changyeh Lee
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Publication number: 20150206488Abstract: The present invention provides a gate driver on array (GOA) circuit and a display panel with the GOA circuit. The driver circuit includes multiple stages of gate driver units and multiple stages of supplementary gate driver units connected in cascade, in which the nth stage gate driver unit includes a driving unit (42) and a pull-down unit (44) and the mth stage supplementary gate driver unit includes a supplementary driving unit (52) and a supplementary pull-down unit (54).Type: ApplicationFiled: January 24, 2014Publication date: July 23, 2015Inventors: Shengdong Zhang, Zhijin Hu, Congwei Liao, Limei Zeng, Changyeh Lee
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Patent number: 9058986Abstract: Designs and fabrication of a FinFET are provided. In one implementation, the fabrication can include forming a dielectric stripe on a substrate; implanting ions to the substrate by using the dielectric stripe as a mask so as to convert a surface layer of the substrate to an amorphous layer; forming an amorphous semiconductor layer on the substrate covering the dielectric stripe and recrystallizing each of the amorphous layer and the amorphous semiconductor layer to be a monocrystalline layer; processing regions beside two ends of the dielectric stripe to form a protective layer, the regions being predesigned as source and drain regions; forming recrystallized semiconductor spacers at two sides of the dielectric stripe uncovered by the protective layer, and forming recrystallized semiconductor blocks on regions covered by the protective layer; removing the dielectric stripe between the spacers so that the spacers can be formed as Fin bodies.Type: GrantFiled: June 13, 2011Date of Patent: June 16, 2015Assignee: PEKING UNIVERSITY SHENZHEN GRADUATE SCHOOLInventors: Shengdong Zhang, Ruqi Han, Dedong Han
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Patent number: 8956926Abstract: Disclosed is a method for manufacturing a self-aligned metal oxide thin film transistor. According to the present invention, a metal oxide semiconductor layer having a high carrier concentration is formed, and then a channel region which is self-aligned with a gate electrode is oxidized by a plasma having oxidbillity so that the channel region has a low carrier concentration and the source and drain regions have high carrier concentrations while the resulting transistor has a self-aligned structure. In addition, the threshold voltage of the transistor is controlled by the conditions under which the channel region of the transistor is subsequently oxidized by plasma having oxidbillity at a low temperature. Therefore, the controllability of the characteristics of the transistor is improved significantly, and the manufacturing process is simplified.Type: GrantFiled: June 13, 2011Date of Patent: February 17, 2015Assignee: Peking University Shenzhen Graduate SchoolInventors: Shengdong Zhang, Xin He, Yi Wang, Dedong Han, Jeng Han
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Patent number: 8766958Abstract: A gate driving circuit unit, a gate driving circuit and a display device are disclosed. The gate driving circuit unit comprises: a first clock signal control module, an input signal control module, a third clock signal control module and a fourth clock signal control module, wherein the first clock signal control module comprises a driving unit and a clock feed-through suppressing unit. The driving unit transmits a first clock signal to an output port after being switched on. The clock feed-through suppressing unit couples the control end of the driving unit to a signal output interface under control of the first clock signal. The input signal control module provides the driving voltage for the driving unit under control of an input pulse signal. The third clock signal control module provides the shutdown voltage for the driving unit.Type: GrantFiled: January 26, 2011Date of Patent: July 1, 2014Assignee: Peking University Shenzhen Graduate SchoolInventors: Shengdong Zhang, Congwei Liao, Changde He, Wenjun Dai
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Publication number: 20140065779Abstract: Designs and fabrication of a FinFET are provided. In one implementation, the fabrication can include forming a dielectric stripe on a substrate; implanting ions to the substrate by using the dielectric stripe as a mask so as to convert a surface layer of the substrate to an amorphous layer; forming an amorphous semiconductor layer on the substrate covering the dielectric stripe and recrystallizing each of the amorphous layer and the amorphous semiconductor layer to be a monocrystalline layer; processing regions beside two ends of the dielectric stripe to form a protective layer, the regions being predesigned as source and drain regions; forming recrystallized semiconductor spacers at two sides of the dielectric stripe uncovered by the protective layer, and forming recrystallized semiconductor blocks on regions covered by the protective layer; removing the dielectric stripe between the spacers so that the spacers can be formed as Fin bodies.Type: ApplicationFiled: June 13, 2011Publication date: March 6, 2014Applicant: Peking University Shenzhen Graduate SchoolInventors: Shengdong Zhang, Ruqi Han, Dedong Han
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Publication number: 20140011329Abstract: Disclosed is a method for manufacturing a self-aligned metal oxide thin film transistor. According to the present invention, a metal oxide semiconductor layer having a high carrier concentration is formed, and then a channel region which is self-aligned with a gate electrode is oxidized by a plasma having oxidbillity so that the channel region has a low carrier concentration and the source and drain regions have high carrier concentrations while the resulting transistor has a self-aligned structure. In addition, the threshold voltage of the transistor is controlled by the conditions under which the channel region of the transistor is subsequently oxidized by plasma having oxidbillity at a low temperature. Therefore, the controllability of the characteristics of the transistor is improved significantly, and the manufacturing process is simplified.Type: ApplicationFiled: June 13, 2011Publication date: January 9, 2014Applicant: Peking University Shenzhen Graduate SchoolInventors: Shengdong Zhang, Xin He, Yi Wang, Dedong Han, Ruqi Han
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Publication number: 20130309808Abstract: Designs and fabrication of dual-gate thin film transistors are provided. An active region and a top gate electrode of the transistor can be made of a transparent thin film material. A photoresist can be coated onto a surface of the transparent conductive thin film for forming the top gate electrode. Light is from the bottom of the substrate during exposure. After the development, a photoresist pattern aligned with the bottom gate electrode is formed on the surface of the conductive thin film. The top gate electrode aligned with the bottom gate electrode is formed by etching the conductive thin film. The bottom gate electrode can be used as a mask, which may save the cost for manufacturing the transistor and improve the accuracy of alignment between the top gate electrode and the bottom gate electrode and the performance of the dual-gate thin film transistor.Type: ApplicationFiled: June 10, 2011Publication date: November 21, 2013Applicant: PEKING UNIVERSITY SHENZHEN GRADUATE SCHOOLInventors: Shengdong Zhang, Xin He, Longyan Wang
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Publication number: 20130122649Abstract: Disclosed is a method for manufacturing a metal oxide thin film transistor. According to the method, an active layer having a high carrier concentration is formed, and then a channel region is oxidized by plasma having oxidbillity so that the channel region has a low carrier concentration while a source region and a drain region have high carrier concentrations. In addition, the threshold voltage of the transistor is controlled by the conditions under which the channel region of the transistor is subsequently oxidized by plasma having oxidbillity at a low temperature. Therefore, the controllability of the characteristics of the transistor is improved significantly, and the manufacturing process is simplified.Type: ApplicationFiled: June 13, 2011Publication date: May 16, 2013Applicant: Peking University Shenzhen Graduate SchoolInventors: Shengdong Zhang, Xin He, Yi Wang, Dedong Han, Ruqi Han
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Publication number: 20120188210Abstract: A gate driving circuit unit, a gate driving circuit and a display device are disclosed. The gate driving circuit unit comprises: a first clock signal control module, an input signal control module, a third clock signal control module and a fourth clock signal control module, wherein the first clock signal control module comprises a driving unit and a clock feed-through suppressing unit. The driving unit transmits a first clock signal to an output port after being switched on. The clock feed-through suppressing unit couples the control end of the driving unit to a signal output interface under control of the first clock signal. The input signal control module provides the driving voltage for the driving unit under control of an input pulse signal. The third clock signal control module provides the shutdown voltage for the driving unit.Type: ApplicationFiled: January 26, 2011Publication date: July 26, 2012Applicant: PEKING UNIVERSITY SHENZHEN GRADUATE SCHOOLInventors: Shengdong Zhang, Congwei Liao, Changde He, Wenjun Dai
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Patent number: 7545008Abstract: A semiconductor device may include a substrate and an insulating layer formed on the substrate. A multi-layer fin may be formed on the insulating layer and may include two semiconducting layers isolated by an insulating layer in vertical direction. A first MOS type device comprising a first source region, a first channel region and a first drain region is arranged on the first semiconducting layer in the multi-layer fin. A second MOS type device comprising a second source region, a second channel region and a second drain region is arranged on the second semiconducting layer in the multi-layer fin. A gate electrode is provided so as to be vertically adjacent to the first and second channel regions.Type: GrantFiled: February 3, 2006Date of Patent: June 9, 2009Assignee: The Hong Kong University of Science and TechnologyInventors: Philip Ching Ho Chan, Man Sun Chan, Xusheng Wu, Shengdong Zhang
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Publication number: 20070181947Abstract: A semiconductor device may include a substrate and an insulating layer formed on the substrate. A multi-layer fin may be formed on the insulating layer and may include two semiconducting layers isolated by an insulating layer in vertical direction. A first MOS type device comprising a first source region, a first channel region and a first drain region is arranged on the first semiconducting layer in the multi-layer fin. A second MOS type device comprising a second source region, a second channel region and a second drain region is arranged on the second semiconducting layer in the multi-layer fin. A gate electrode is provided so as to be vertically adjacent to the first and second channel regions.Type: ApplicationFiled: February 3, 2006Publication date: August 9, 2007Applicant: The Hong Kong University of Science and TechnologyInventors: Philip Ching Ho Chan, Man Sun Chan, Xusheng Wu, Shengdong Zhang