Abstract: A wireless local area network (WLAN) transceiving integrated circuit services voice communications in a WLAN with at least one other wireless device and includes a WLAN interface, a transcoder, and a switch box. The WLAN interface wirelessly communicates with at least one wireless device to receive inbound packetized audio data from the at least one wireless device and to transmit outbound packetized audio data to the at least one wireless device. The transcoder receives the inbound packetized audio data and converts the inbound packetized audio data to inbound Pulse Code Modulated (PCM) WLAN audio data. The WLAN interface also receives outbound PCM WLAN audio data and converts the outbound PCM WLAN audio data to the outbound packetized audio data. The switch box operably couples between the transcoder and a PCM bus, to which an audio COder/DECoder (CODEC) couples. A speaker and a microphone coupled to the audio CODEC.

Abstract: A microprocessor system architecture is disclosed which allows for the selective execution of programmed ROM microcode or, alternatively, RAM microcode if there has been a correction or update made to the ROM microcode originally programmed into the system. Patched or updated RAM microcode is utilized or executed only to the extent of changes to the ROM microcode, otherwise the ROM microcode is executed in its normal fashion. When a patch is received, it is loaded into system RAM along with instructions or other appropriate signals to direct the execution of the patched or updated microcode from RAM instead of the existing ROM microcode. Various methods are presented for selecting the execution of the appropriate microcode depending upon whether there have been changes made to it.

Abstract: A wireless local area network (WLAN) transceiving integrated circuit includes a WLAN interface, an input buffer, an input buffer controller, and a processor. The WLAN transceiving integrated circuit may also include an output buffer, an output buffer controller, a transcoder, and/or an audio Coder-Decoder (CODEC). The WLAN transceiving integrated circuit is installed in a WLAN device that services voice communications. The input buffer receives packetized audio data from the WLAN interface. When the input buffer satisfies a buffer vacancy threshold, the processor and the input buffer controller cooperatively operate to fill at least a portion of the input buffer with packetized audio data. The processor copies packetized audio data from the input buffer and fills the input buffer with the copied packetized audio data to maintain an audio pattern in the input buffer. The input buffer controller fills the input buffer when the processor is available and after copying/filling is no longer effective.

Abstract: A wireless local area network (WLAN) transceiving integrated circuit services voice communications in a WLAN with at least one other WLAN device and includes a WLAN interface, a transcoder, and a switch box. The WLAN interface wirelessly communicates with at least one WLAN device to receive inbound packetized audio data from the at least one WLAN device and to transmit outbound packetized audio data to the at least one WLAN device. The transcoder receives the inbound packetized audio data and converts the inbound packetized audio data to inbound Pulse Code Modulated (PCM) WLAN audio data. The WLAN interface also receives outbound PCM WLAN audio data and converts the outbound PCM WLAN audio data to the outbound packetized audio data. The switch box operably couples between the transcoder and a PCM bus, to which an audio COder/DECoder (CODEC) couples. A speaker and a microphone coupled to the audio CODEC.

Abstract: A microprocessor system architecture is disclosed which allows for the selective execution of programmed ROM microcode or, alternatively, RAM microcode if there has been a correction or update made to the ROM microcode originally programmed into the system. Patched or updated RAM microcode is utilized or executed only to the extent of changes to the ROM microcode, otherwise the ROM microcode is executed in its normal fashion. When a patch is received, it is loaded into system RAM along with instructions or other appropriate signals to direct the execution of the patched or updated microcode from RAM instead of the existing ROM microcode. Various methods are presented for selecting the execution of the appropriate microcode depending upon whether there have been changes made to it.

Abstract: A wireless local area network (WLAN) transceiving integrated circuit services voice communications in a WLAN with at least one other WLAN device. The WLAN transceiving integrated circuit includes a WLAN interface, an input buffer, a transcoder, and a processor. The WLAN interface wirelessly communicates with the at least one WLAN device to receive packetized audio data from the at least one WLAN device. The input buffer operably couples to the WLAN interface and receives the packetized audio data from the WLAN interface. The transcoder converts the packetized audio data to Pulse Code Modulated (PCM) audio data and outputs the PCM audio data to a coupled audio COder/DECoder (CODEC) such that the PCM audio data is substantially temporally aligned with Radio Frequency (RF) slots of the WLAN interface.

Abstract: A wireless local area network (WLAN) transceiving integrated circuit services voice communications in a WLAN with at least one other WLAN device. The WLAN transceiving integrated circuit includes a WLAN interface, an input buffer, a transcoder, and a processor. The WLAN interface wirelessly communicates with the at least one WLAN device to receive packetized audio data from the at least one WLAN device. The input buffer operably couples to the WLAN interface and receives the packetized audio data from the WLAN interface. The transcoder operably couples to the input buffer and receives the packetized audio data from the input buffer. The transcoder converts the packetized audio data to Pulse Code Modulated (PCM) audio data and outputs the PCM audio data to a coupled audio COder/DECoder (CODEC). The processor operably couples to the WLAN interface, the input buffer, and the transcoder.

Abstract: A microprocessor system architecture is disclosed which allows for the selective execution of programmed ROM microcode or, alternatively, RAM microcode if there has been a correction or update made to the ROM microcode originally programmed into the system. Patched or updated RAM microcode is utilized or executed only to the extent of changes to the ROM microcode, otherwise the ROM microcode is executed in its normal fashion. When a patch is received, it is loaded into system RAM along with instructions or other appropriate signals to direct the execution of the patched or updated microcode from RAM instead of the existing ROM microcode. Various methods are presented for selecting the execution of the appropriate microcode depending upon whether there have been changes made to it.

Abstract: A microprocessor system architecture is disclosed which allows for the selective execution of programmed ROM microcode or, alternatively, RAM microcode if there has been a correction or update made to the ROM microcode originally programmed into the system. Patched or updated RAM microcode is utilized or executed only to the extent of changes to the ROM microcode, otherwise the ROM microcode is executed in its normal fashion. When a patch is received, it is loaded into system RAM along with instructions or other appropriate signals to direct the execution of the patched or updated microcode from RAM instead of the existing ROM microcode. Various methods are presented for selecting the execution of the appropriate microcode depending upon whether there have been changes made to it.

Abstract: A wireless (radio) receiver receives RF signals carrying data synchronized with a first clock. The wireless receiver demodulates the RF signals to extract the data signals and the first clock signals. The wireless receiver uses the first clock signals as write signals to write the data signals in a first-in first-out memory device (FIFO). The data signals stored in the FIFO may be read out with read signals synchronized to a second clock. In one example, a host associated with the wireless receiver reads out data signals stored in the FIFO with read signals synchronized to the system clock of the host receiver. In another example, the wireless receiver includes a data processing circuit (e.g., including forward error correction, de-whitening, and cyclical redundancy check circuits) that reads out data signals stored in the FIFO with read signals synchronized to the system clock of the wireless receiver.

Abstract: A treated substrate with improved availability of a beneficial component for transfer to a target surface and methods for making the same are described. The substrate has a contacting surface with a beneficial component that is transferred from the contacting surface to a target surface during use of the article. The beneficial component is applied to the article in such a way as to “Top-Bias” the component on or near the contacting surface of the article.

Abstract: A method and system for performing switch operations utilize non-architectural registers to store context information. Data in a first context register on a peripheral system is accessed (e.g., read or write) until a host computer provides a new index value to an index register on the peripheral system. A context switch occurs, and the context register associated with the new index value is accessed. In some embodiments a system that performs context switching includes a host computer, at least one peripheral system coupled to the host computer, an interface between the host computer and the peripheral system, and a register access circuit coupled to the host computer. The register access circuit is configured to access data in a first or a second register on the peripheral system if the first or a second index value, respectively, is provided by the host computer.

Abstract: A microprocessor memory architecture including a read-only memory (ROM) with programmed microcode and a random access memory (RAM) capable of storing microcode and one or more data bits used for the selection of corresponding ROM or RAM microcode for execution. A multiplexer receives input signals from both the ROM microcode and RAM microcode, and a control signal which is one or more RAM data bits is used to select from the RAM or ROM microcode inputs for further execution by the microprocessor.

Abstract: A wireless (radio) receiver receives RF signals carrying data synchronized with a first clock. The wireless receiver demodulates the RF signals to extract the data signals and the first clock signals. The wireless receiver uses the first clock signals as write signals to write the data signals in a first-in first-out memory device (FIFO). The data signals stored in the FIFO may be read out with read signals synchronized to a second clock. In one example, a host associated with the wireless receiver reads out data signals stored in the FIFO with read signals synchronized to the system clock of the host receiver. In another example, the wireless receiver includes a data processing circuit (e.g., including forward error correction, de-whitening, and cyclical redundancy check circuits) that reads out data signals stored in the FIFO with read signals synchronized to the system clock of the wireless receiver.

Abstract: A microprocessor memory architecture including a read-only memory (ROM) with programmed microcode and a random access memory (RAM) capable of storing microcode and one or more data bits used for the selection of corresponding ROM or RAM microcode for execution. A multiplexer receives input signals from both the ROM microcode and RAM microcode, and a control signal which is one or more RAM data bits is used to select from the RAM or ROM microcode inputs for further execution by the microprocessor.

Abstract: A wireless (radio) receiver receives RF signals carrying data synchronized with a first clock. The wireless receiver demodulates the RF signals to extract the data signals and the first clock signals. The wireless receiver uses the first clock signals as write signals to write the data signals in a first-in first-out memory device (FIFO). The data signals stored in the FIFO may be read out with read signals synchronized to a second clock. In one example, a host associated with the wireless receiver reads out data signals stored in the FIFO with read signals synchronized to the system clock of the host receiver. In another example, the wireless receiver includes a data processing circuit (e.g., including forward error correction, de-whitening, and cyclical redundancy check circuits) that reads out data signals stored in the FIFO with read signals synchronized to the system clock of the wireless receiver.

Abstract: A microprocessor system architecture is disclosed which allows for the selective execution of programmed ROM microcode or, alternatively, RAM microcode if there has been a correction or update made to the ROM microcode originally programmed into the system. Patched or updated RAM microcode is utilized or executed only to the extent of changes to the ROM microcode, otherwise the ROM microcode is executed in its normal fashion. When a patch is received, it is loaded into system RAM along with instructions or other appropriate signals to direct the execution of the patched or updated microcode from RAM instead of the existing ROM microcode. Various methods are presented for selecting the execution of the appropriate microcode depending upon whether there have been changes made to it.

Abstract: A wireless local area network (WLAN) transceiving integrated circuit includes a WLAN interface, an input buffer, an input buffer controller, and a processor. The WLAN transceiving integrated circuit may also include an output buffer, an output buffer controller, a transcoder, and/or an audio Coder-Decoder (CODEC). The WLAN transceiving integrated circuit is installed in a WLAN device that services voice communications. The input buffer receives packetized audio data from the WLAN interface. When the input buffer satisfies a buffer vacancy threshold, the processor and the input buffer controller cooperatively operate to fill at least a portion of the input buffer with packetized audio data. The processor copies packetized audio data from the input buffer and fills the input buffer with the copied packetized audio data to maintain an audio pattern in the input buffer. The input buffer controller fills the input buffer when the processor is available and after copying/filling is no longer effective.

Abstract: A wireless local area network (WLAN) transceiving integrated circuit services voice communications in a WLAN with at least one other WLAN device and includes a WLAN interface, a transcoder, and a switch box. The WLAN interface wirelessly communicates with at least one WLAN device to receive inbound packetized audio data from the at least one WLAN device and to transmit outbound packetized audio data to the at least one WLAN device. The transcoder receives the inbound packetized audio data and converts the inbound packetized audio data to inbound Pulse Code Modulated (PCM) WLAN audio data. The WLAN interface also receives outbound PCM WLAN audio data and converts the outbound PCM WLAN audio data to the outbound packetized audio data. The switch box operably couples between the transcoder and a PCM bus, to which an audio COder/DECoder (CODEC) couples. A speaker and a microphone coupled to the audio CODEC.

Abstract: A wireless local area network (WLAN) transceiving integrated circuit services voice communications in a WLAN with at least one other WLAN device. The WLAN transceiving integrated circuit includes a WLAN interface, an input buffer, a transcoder, and a processor. The WLAN interface wirelessly communicates with the at least one WLAN device to receive packetized audio data from the at least one WLAN device. The input buffer operably couples to the WLAN interface and receives the packetized audio data from the WLAN interface. The transcoder operably couples to the input buffer and receives the packetized audio data from the input buffer. The transcoder converts the packetized audio data to Pulse Code Modulated (PCM) audio data and outputs the PCM audio data to a coupled audio COder/DECoder (CODEC). The processor operably couples to the WLAN interface, the input buffer, and the transcoder.