Abstract: A treated substrate with improved availability of a beneficial component for transfer to a target surface and methods for making the same are described. The substrate has a contacting surface with a beneficial component that is transferred from the contacting surface to a target surface during use of the article. The beneficial component is applied to the article in such a way as to “Top-Bias” the component on or near the contacting surface of the article.

Abstract: A protocol accelerator includes a first processor connected to a host machine and programmed to provide a first protocol layer for data to be sent to a destination device. A second processor is connected to the first processor and is programmed to provide a second protocol layer for the data. A third processor is connected to the second processor and is programmed to provide a third protocol layer for the data. The third processor is connected to a network by which the data is sent to the destination device. The system can be configured for any number of protocol layers, by providing a dedicated processor in a pipelined configuration for each respective layer.

Abstract: A central processing unit (CPU) repeatedly interrupts execution of software to save the CPU state, i.e. contents of various storage elements internal to the CPU, until an error occurs during the execution. On occurrence of the error, the CPU once again saves state and only then passes control to a handler in the software for handling the error. The state saving steps can be implemented in a computer process by use of a timer interrupt or by use of system management, or ICE breakpoint instructions that are included in the x86 instruction set. Errors can be debugged off-line in a development system, for example, by use of an in-circuit emulator to load the saved CPU states sequentially into the development system, thereby to recreate the error condition. Errors can also be debugged proactively, even before the error occurs, by use of a number of known-to-be-erroneous instructions and corresponding fix instructions.

Abstract: A microprocessor memory architecture including a read-only memory (ROM) with programmed microcode and a random access memory (RAM) capable of storing microcode and one or more data bits used for the selection of corresponding ROM or RAM microcode for execution. A multiplexer receives input signals from both the ROM microcode and RAM microcode, and a control signal which is one or more RAM data bits is used to select from the RAM or ROM microcode inputs for further execution by the microprocessor.

Abstract: A central processing unit (CPU) repeatedly interrupts execution of software to save the CPU state, i.e. contents of various storage elements internal to the CPU, until an error occurs during the execution. On occurrence of the error, the CPU once again saves state and only then passes control to a handler in the software for handling the error. The state saving steps can be implemented in a computer process by use of a timer interrupt or by use of system management, or ICE breakpoint instructions that are included in the x86 instruction set. Errors can be debugged off-line in a development system, for example, by use of an in-circuit emulator to load the saved CPU states sequentially into the development system, thereby to recreate the error condition. Errors can also be debugged proactively, even before the error occurs, by use of a number of known-to-be-erroneous instructions and corresponding fix instructions.

Abstract: A novel distributed arbitration apparatus in accordance with this invention includes a plurality of electrical devices, such as Industry Standard Architecture (ISA) hub cards, that independently determine availability of a shared resource, such as a bus that interconnects the devices, by use of an arbiter. When a circuit in an electrical device needs to use the bus, the circuit drives a request signal active to an arbiter, for example, in the form of a programmable logic device, such as a Programmable Array Logic (PAL.TM.) device included in the electrical device. The arbiter in turn transmits the request signal to all other arbiters. Therefore, each arbiter receives and monitors request signals from all circuits. If only one request signal is active at a given time, all arbiters receive the active request signal and each arbiter drives an acknowledge signal active to the respective local circuit. The circuit that requested the shared resource then uses the resource.

Abstract: According to the invention, a method for valuing the contribution of IP Blocks into integrated circuit (IC) designs includes implementing a novel concept for valuing technical and economic factors. Based upon such factors, users can more reliably value, select and use IP Blocks for their IC design that furthers their objectives. In an embodiment according to the present invention, a method for determining a group of IP Blocks from a plurality of IP Blocks to incorporate into a circuit design includes the steps of determining a circuit architecture to be implemented by the circuit design, and determining a valuation for implementing the circuit architecture.

Abstract: An adaptive computing device includes a processing unit connected to receive instructions for execution and a random access memory storing microcode for access by the processing unit to carry out steps for executing the instructions. The microcode is loaded into the random access memory from a source of microcodes tailored for efficient execution of the instructions received by the processing unit. The adaptive computing unit may further include control logic responsive to the instructions for execution to request a loading of microcode into the random access memory from the source of microcodes. The adaptive computing unit may further include control logic responsive to signals generated external to the computing unit to request loading of microcode into the random access memory from the source of microcodes.

Abstract: A user-removable CPU card includes a microprocessor and a bus bridge memory controller that allows the use of the microprocessor as a central processing unit of an electrical device (e.g. notebook PC or desktop PC). The user-removable CPU card includes a first connector that can be detachably coupled to a second connector in the electrical device, when the user-removable CPU card is inserted through an opening of the electrical device. When the electrical device is powered up subsequent to such insertion, the microprocessor on the user-removable CPU card functions as the central processing unit. Inclusion of a central processing unit of a computing device on a user-removable CPU card allows easy replacement of the CPU, for example, by simply opening a door and operating an eject mechanism, without disassembly of the housing.

Abstract: A computer network includes a plurality of servers, each of the plurality of servers operating under one of a plurality of operating systems, and a client workstation including a single boot ROM containing instructions for identifying each of the plurality of servers by address and by type of operating system, and selecting one of the identified servers by address and type for booting on the network.

Abstract: A system and method for providing a microprocessor with a software accessible serial number. A plurality of programmable fuses on the processor are encoded with a value representative of a serial number. Circuitry is provided on the processor for transferring the value encoded on the programmable fuses to a machine specific or general purpose register or storage device. The machine specific or general purpose register or storage unit is software accessible.

Abstract: A method of executing a program includes reading a next operation of an executing program and determining if a given pointer corresponding to the next operation is stored in a pointer table. If the given pointer is stored in the pointer table, an instruction identified by the given pointer is executed in a processor. However, if the given pointer is not stored in the pointer table, a replaceable pointer in the pointer table is identified and replaced by the given pointer. Instructions corresponding to the given pointer are also imported into a processor instruction unit from a supplemental storage area and subsequently executed by the processor. The instructions can comprise microcode or a portion of a programmable gate array. In the latter case, the supplemental storage area can store gate array programming instructions for use in reprogramming the instructions in the processor.

Abstract: A central processing unit (hereinafter "CPU") has a number of functional units and a tuning port for modifying one or more parameters of the functional units (hereinafter "tunable units"). The combination (also called a "tuning assembly") formed by a tuning port and the tunable units allows a CPU to be fine tuned, i.e. take on different configuration profiles (as defined by the tunable units' parameters) for efficiently executing different application programs. Therefore, a CPU that includes a tuning assembly as described herein can take on a first configuration profile capable of most efficiently executing a first application program such as a computer game, and can take on a second configuration profile capable of most efficiently executing a second application program such as a spreadsheet and so on. The CPU's configuration profile can be changed even during the execution of an application program by changing the tunable units' parameters.

Abstract: A method and apparatus for providing a microprocessor serial number. A small, nonvolatile random access memory is packaged with the CPU die to provide a storage space for a CPU serial number which can be programmed before leaving the factory. Both the CPU die and the nonvolatile RAM die reside within the cavity of the package. Connection between the two die is provided by conventional wire bonding.

Abstract: A system and method for facilitates a fast transmission of packet information into the buffers without unnecessary delays, thereby increasing overall system performance. The method and system comprises sending a packet of information located in a local buffer to a media, generating an interrupt signal indicating a completed transfer of the packet to the media and availability of the local buffer for receiving a next packet, and sending the next packet of information from a queue to the local buffer in response to the interrupt signal, wherein the generation of the interrupt signal after each data packet is transmitted to the media does not affect the overall operation of the processing system.

Abstract: A novel hub-network adapter device has a substrate that supports (1) a network interface circuit and (2) a repeater circuit, both of which are directly connected to each other by a number of electrical conductors also supported by the substrate. The network interface circuit includes (1) a network port that is directly connected to a repeater port of the repeater circuit and (2) a number of bus terminals that are coupled to a bus of a file server personal computer. In addition to the directly connected repeater port, the repeater circuit includes a number of repeater ports that are connected to hub's repeater port connectors also mounted on the substrate. The novel direct connection of a repeater port and a network port eliminates the cost of conventional parts, such as a transceiver or an ethernet cable.

Abstract: A method for choosing a particular server on a network and performing a remote boot by a client, the network including a plurality of servers operating in accordance with a plurality of network operating systems, includes identifying each of the plurality of servers by address and by type of operating system, and selecting one of the identified servers by address and type for booting on the network. Identifying further includes sending a FIND frame from the client to the network, and receiving a FOUND frame from each of the plurality of servers. A remote program load protocol followed by the server according to the FOUND frame is determined.

Abstract: A byte swapping device includes first and second data ports and data path logic coupled between the first and second data ports. The byte swapping device is employed in a data processing system comprising a data storage device configured to store bytes of data, a processor which reads data from the data storage device and writes data to the data storage device, and the byte swapping device coupled between the data storage device and the processor. The first data port is coupled to the data storage device and the second data port is coupled to the processor. The storage device is typically a system memory or peripheral device controller. The processor processes data in a first endian format, i.e., big-endian or little-endian format, and at least a portion of the data stored in the data storage device is in the opposite byte ordering. The byte swapping device selectively byte swaps data transferred between the processor and storage device.

Abstract: A microprocessor with automatic and dynamic partname determination including performance number. The microprocessor includes circuitry that measures a core clock frequency for the microprocessor and circuitry that determines a performance indication for the microprocessor in response to the measured core clock frequency.

Abstract: A novel identity apparatus in the form of, for example, a cable or a system board has a number of connectors, each connector including one or more "identity" terminals, that are used to uniquely identify an electrical device attached to the connector. The identity apparatus eliminates jumpers or dip switches conventionally used in an electrical device to provide an identity to the electrical device. An identity cable's identity terminals are pulled up to reference voltage Vcc by the attached electrical device that also senses the voltage at the identity terminals to determine identity. The identity cable's connector includes a "ground" terminal that is coupled to ground by the attached electrical device. Each identity terminal of a cable is couplable (i.e. can be coupled) inside the identity cable to ground or alternatively left unconnected, to thereby indicate a logic state "1" or a logic state "0" respectively.