Abstract: A method for compiling a software program and executing the program on a data processing system which performs conversion between data formatted in differing endian formats, namely big-endian and little-endian formats, also known as byte swapping. The data processing system comprises a data storage device, such as system memory, a processor, and a byte swapping device coupled between the data storage device and the processor. Data conversion apertures, or ranges, are defined in the processor address space and the processor provides address signals to the byte swapping device. The byte swapping device selectively byte swaps data transferred between the processor and storage device based upon the relationship between the addresses received by the byte swapping device and the data conversion apertures.

Abstract: A system is described for facilitating operation of a peripheral bus, such as a PCI bus, at a higher clock frequency. Each of the devices resident on the PCI bus include certain configuration registers, including MIN.sub.-- GNT and MAX.sub.-- LAT, which provide configuration parameters to various system resources. In addition, each of the devices resident on the PCI bus include a status register with a dedicated 66 MHzCAPABLE bit. The dedicated status bit indicates whether the PCI device is capable of operating in a 66 MHz environment. As a result, each device can be polled during system initialization to determine if all of the PCI devices will support 66 MHz operation. If the system determines that the clock frequency will change due to a change in the system configuration (such as PCI devices being added or removed from the PCI bus), the configuration registers of each of the PCI devices can be modified to insure proper operation at the new clock frequency.

Abstract: A computer process transforms a "general purpose" central processing unit (hereinafter "CPU") into one of a number of possible "special purpose" CPUs by changing operation of circuitry in the CPU. Changing operation of CPU circuitry as described herein "fine tunes" behavior of the CPU, e.g. provides resources and environment most suitable for execution of a specific application program, or even a portion of an application program. The computer process performs the steps of: checking whether the CPU has a tunable unit, waiting for a triggering event indicating a need for fine tuning, reading one or more statistics on the performance of the CPU, comparing the read statistics with corresponding predetermined statistics, determining a multi-valued parameter signal depending on the comparison, driving the determined parameter signal to the tunable unit and changing operation of circuitry in the tunable unit depending on the received parameter signal, thereby to fine tune operation of the tunable unit and the CPU.

Abstract: A system and method for detecting and gracefully recovering from a peripheral device fault has been disclosed. The method detects whether a peripheral device has suffered from a peripheral device fault. Where the peripheral device fault has occurred, the method determines whether any of a plurality of processes executable by the peripheral device is currently being executed by the peripheral device. The plurality of processes comprises those process which could result in significant loss of data, loss of connection to a network or adversely affect the performance of the peripheral device if the peripheral device is reset during execution of any of the plurality of processes. If none of the plurality of processes is being executed by the peripheral device, the method automatically resets the peripheral device. According to the method and system disclosed, peripheral devices can be made to recover from faults without user intervention, without loss of connection to any networks, and with minimal loss of data.

Abstract: A system and method for providing information regarding system support capabilities to a processor. A computer system includes a processing unit, a main memory and a first plurality of peripherals coupled to a first bus. A bus bridge couples the first bus to a second bus and a second plurality of support peripherals are coupled to the second bus. The processing unit is capable of providing requests for system support information to the bus bridge and the first and second plurality support peripherals. The peripherals are configured to provide responses to the request. The processing unit stores the responses and uses the information received to enable and disable its functional units or the peripheral's functional units accordingly. In one embodiment, the requests and information are provided along a dedicated serial interface. In another, the requests and information are provided as specialized bus cycles along the CPU bus.

Abstract: A method and apparatus for software to access a microprocessor serial number. Provision of the serial number allows the manufacturer better control over its product and also permits software vendors to register their products. The serial number is encrypted using a pair of encryption keys to prevent unauthorized changes. At least one of the encryption keys is itself encoded to prevent unauthorized access, while permitting software to access the serial number.

Abstract: A method and apparatus for providing, maintaining and upgrading the software lock of a microprocessor. When a processor upgrade occurs, software that was serialized to the previously installed processor detects that it is running on an unauthorized processor. The software initiates a reauthorization process based on a reauthorization use profile. The temporary re-enabling of the software is allowed if the authorization service is not available.

Abstract: A jack has a side opening that allows light from a light emitter that is mounted adjacent to the side opening to enter the jack's cavity and emerge from the jack's front opening that is used for insertion of a plug. In one embodiment, when a plug is inserted into the jack, a transparent portion of the plug allows the light to emerge from a posterior end of the plug to provide a visible indication of the state of the connection between the jack and the plug. Emergence of light from the jack's front opening results in saving space on a jack panel because panel space conventionally used for a LED is no longer needed. The side opening is located adjacent to the jack's bottom surface that is adjacent to a printed circuit board (PCB) on which the jack is mounted. In one embodiment, the light emitter is mounted on the PCB near the side opening between the jack's bottom surface and the PCB's top surface.

Abstract: An apparatus which includes a swivel base formed of a first plate and a second plate. The first and second plates each have a central aperture which is defined by a hook-shaped section of the second plate which extends over an interior edge of the first plate defining the first plate's central aperture. The hook-shaped section is preferably circumferentially continuous and fixes the first and second plates together while allowing for sliding engagement between the first and second plates. Bearing members, such as circumferentially spaced ball bearings, are provided externally to the hook section and between the plates to facilitate sliding and load distribution. One of the plates includes hollow reception ports for holding the bearing circumferentially in place with respect to that plate while the opposite plate has a continuous riding ring in which the bearings are free to rotate.

Abstract: A method and apparatus for encrypting and decrypting a microprocessor serial number. First and second encryption keys and a serial number are provided in microprocessor machine specific registers. The serial number is encrypted using the first key. The encrypted serial number is encrypted using the second key. The first encryption key may be encrypted along with the serial number using the second key. The double encrypted serial number is then stored in memory provided for that purpose.

Abstract: A novel distributed arbitration apparatus in accordance with this invention includes a plurality of electrical devices, such as Industry Standard Architecture (ISA) hub cards, that independently determine availability of a shared resource, such as a bus that interconnects the devices, by use of an arbiter. When a circuit in an electrical device needs to use the bus, the circuit drives a request signal active to an arbiter, for example, in the form of a programmable logic device, such as a Programmable Array Logic (PAL.TM.) device included in the electrical device. The arbiter in turn transmits the request signal to all other arbiters. Therefore, each arbiter receives and monitors request signals from all circuits. If only one request signal is active at a given time, all arbiters receive the active request signal and each arbiter drives an acknowledge signal active to the respective local circuit. The circuit that requested the shared resource then uses the resource.

Abstract: A user-removable CPU card includes a microprocessor and a bus bridge memory controller that allows the use of the microprocessor as a central processing unit of an electrical device (e.g. notebook PC or desktop PC). The user-removable CPU card includes a first connector that can be detachably coupled to a second connector in the electrical device, when the user-removable CPU card is inserted through an opening of the electrical device. When the electrical device is powered up subsequent to such insertion, the microprocessor on the user-removable CPU card functions as the central processing unit. Inclusion of a central processing unit of a computing device on a user-removable CPU card allows easy replacement of the CPU, for example, by simply opening a door and operating an eject mechanism, without disassembly of the housing.

Abstract: A method and system for resetting a peripheral device which could use a variety of buses have been disclosed. The method and system determine what bus type the peripheral device has. The method and system then automatically execute a reset process capable of resetting the peripheral device having that bus type. A beneficial aspect of this invention is allowing a peripheral device to gracefully recover from a fault. In this aspect, the method detects whether a peripheral device fault has occurred. Where the fault has occurred, the method determines whether any of a plurality of processes executable by the peripheral device is being executed. The processes comprise those processes which could result in significant loss of data, loss of connection to a network, or adversely affect performance if the peripheral device is reset during execution. If none of the processes is being executed, the method automatically resets the peripheral device.

Abstract: An apparatus which includes a swivel base formed of a first plate and a second plate. The first and second plates each have a central aperture which is defined by a hook-shaped section of the second plate which extends over an interior edge of the first plate defining the first plate's central aperture. The hook-shaped section is preferably circumferentially continuous and fixes the first and second plates together while allowing for sliding engagement between the first and second plates. Bearing members, such as circumferentially spaced ball bearings are provided externally to the hook section and between the plates to facilitate sliding and load distribution. One of the plates includes hollow reception ports for holding the bearing circumferentially in place with respect to that plate while the opposite plate has a continuous riding ring in which the bearings are free to rotate.

Abstract: A system is described for facilitating operation of a peripheral bus, such as a PCI bus, at different clock frequencies. One embodiment includes an enable line (66 MHzENABLE) connected to each of the devices resident on the PCI bus. The enable line is passively pulled high through a pull-up resistor if all devices resident on the PCI bus can support high frequency operation (such as, for example, 66 MHz). If any device cannot support high frequency operation, the device internally connects the enable line to ground in accordance with present industry specifications. Thus, the enable line will be passively high only if all of the PCI devices support high frequency operation, but will be asserted low if any device cannot support high frequency operation. The invention also includes a dedicated status bit to permit the system to warn the operator of discrepancies between device and bus capabilities.

Abstract: A system and method for controlling a peripheral bus clock signal through a master and/or slave device is provided that accommodates a power conservation (or "clock run") scheme in which a peripheral bus clock signal may be stopped, for example, by a power management unit or other central resource. The clock run feature is enabled or disabled by the system during or immediately following system initialization, based upon the ability of the peripheral bus components to support the clock run feature. The system includes status and command registers to provide an indication of whether each of the peripheral bus devices can support the power conservation scheme. The status and command registers both include a bit dedicated to the clock run function. The status register bit is set based upon whether that particular device can support the clock run function.

Abstract: A printed circuit board (PCB) capable of operating at first and second predetermined voltage levels including a plurality of metal layers, one of the metal layers being divided to provide two electrically isolated sections, the two electrically isolated sections being on substantially the same plane; one of the electrically isolated sections being associated with the first predetermined voltage level and the other of the electrically isolated sections being associated with the second predetermined voltage level. The PCB includes a first plurality of signal pins coupled to the one of the electrically isolated sections. The PCB also includes at least one capacitor coupled to a ground plane, the first plurality of signal pins and the one of the electrically isolated metal sections, wherein an alternating current path is provided. The PCB in a preferred embodiment is an expansion board utilized in a personal computer.

Abstract: A printed circuit board (PCB) capable of operating at first and second predetermined voltage levels including a plurality of metal layers, one of the metal layers being divided to provide two electrically isolated sections, the two electrically isolated sections being on substantially the same plane; one of the electrically isolated sections being associated with the first predetermined voltage level and the other of the electrically isolated sections being associated with the second predetermined voltage level. The PCB includes a first plurality of signal pins coupled to the one of the electrically isolated sections. The PCB also includes at least one capacitor coupled to a ground plane, the first plurality of signal pins and the one of the electrically isolated metal sections, wherein an alternating current path is provided. The PCB in a preferred embodiment is an expansion board utilized in a personal computer.

Abstract: Methods and apparatus are disclosed for transferring data to and from the Local Bus of a reduced instruction set computer (RISC) system, to which a first set of high performance devices, including at least one central processor ("CPU"), is attached, and a Remote Bus, to which a second set of relatively lower performance devices is attached, in a manner that does not limit the RISC processor's performance. According to the preferred embodiment of the invention, a RISC architecture is disclosed that includes a novel data transfer controller ("DTC"), or set of DTCs, suitable for performing the aforesaid data transfer function between the high performance Local Bus and one or more Remote Buses to which complete subsystems or peripherals, typically having different (and lower) performance characteristics, are attached. The resulting RISC arthitecture permits commercially available peripherals and subsystems to be used with high performance RISC processors without limiting RISC system performance.

Abstract: Methods and apparatus are disclosed for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU") is attached, and a second bus, to which a second set of relatively lower performance devices is attached. More particularly the invention accomplishes the above transfer function in a manner that facilitates communication between the first and second set of devices from the compartively lower performance of the second set of devices. According to the preferred embodiment of the invention, a data transfer controller i.e., ("DTC") is disclosed that includes a set of direct memory access ("DMA") channels and an input/output controller comprising a set of address mapped I/O ports.