Abstract: A semiconductor device structure is provided. The semiconductor device structure includes first nanostructures and second nanostructures stacked in a vertical direction over a substrate, and a first dummy fin structure between the first nanostructures and the second nanostructures. The semiconductor device structure includes a first gate structure formed over the first nanostructures, wherein the first gate structure includes a gate dielectric layer, and the gate dielectric layer is in direct contact with a sidewall surface of the first dummy fin structure.

Abstract: The present disclosure provides a method of forming a semiconductor structure with a metal gate. The semiconductor structure is formed by first fabricating fins over a semiconductor substrate, followed by a formation of a source and a drain recess. A source and a drain region may then be deposited into the source and the drain recess. The gate structure may be deposited into the region between the fins. The gate structure includes dielectric and metallic layers. In the regions between the fins, the gate structure is isolated from the source and the drain region by an insulating layer.

Abstract: Embodiments of the present disclosure provide a method of forming sidewall spacers by filling a trench between a hybrid fin and a semiconductor fin structure. The sidewall spacer includes two fin sidewall spacer portions connected by a gate sidewall spacer portion. The fin sidewall spacer portion has a substantially uniform profile to provide uniform protection for vertically stacked channel layers and eliminate any gaps and leaks between inner spacers and sidewall spacers.

Abstract: A method includes etching a hybrid substrate to form a recess extending into the hybrid substrate. The hybrid substrate includes a first semiconductor layer having a first surface orientation, a dielectric layer over the first semiconductor layer, and a second semiconductor layer having a second surface orientation different from the first surface orientation. After the etching, a top surface of the first semiconductor layer is exposed to the recess. A spacer is formed on a sidewall of the recess. The spacer contacts a sidewall of the dielectric layer and a sidewall of the second semiconductor layer. An epitaxy is performed to grow an epitaxy semiconductor region from the first semiconductor layer. The spacer is removed.

Abstract: Gate isolation techniques disclosed herein form gate isolation fins to isolate metal gates of multigate devices from one another before forming the multigate devices, and in particular, before forming the metal gates of the multigate devices. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A gate isolation fin, which separates the first metal gate and the second metal gate, includes a dielectric feature having a first dielectric layer having a first dielectric constant (e.g., a low-k dielectric core) and a second dielectric layer (e.g., a high-k dielectric shell) surrounding the first dielectric layer. The second dielectric layer has a second dielectric constant that is greater than the first dielectric constant.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a plurality of nanowire structures over a channel region of a semiconductor fin structure, a source/drain feature on a source/drain region of the semiconductor fin structure, and a dielectric fin structure spaced apart from the source/drain feature and the semiconductor fin structure. A top surface of the dielectric fin structure is higher than a top surface of a bottommost one of the nanowire structures, and a bottom surface of the dielectric fin structure is lower than a bottom surface of the source/drain feature.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first fin structure over a base region of a semiconductor substrate. A first plurality of semiconductor channel structures stacked vertically with one another over the base region of the semiconductor substrate. A first width of the first fin structure is different from a second width of the first plurality of semiconductor channel structures. A gate structure extends from the first fin structure to the first plurality of semiconductor channel structures.

Abstract: According to an exemplary embodiment, a method of forming a vertical structure is provided. The method includes the following operations: providing a substrate; providing the vertical structure having a source, a channel, and a drain over the substrate; shrinking the source and the channel by oxidation; forming a metal layer over the drain of the vertical structure; and annealing the metal layer to form a silicide over the drain of the vertical structure.

Abstract: Semiconductor devices and methods are provided. A method according to the present disclosure includes receiving a substrate that includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; forming a plurality of fins over the third semiconductor layer; forming a trench between two of the plurality of fins; depositing a dummy material in the trench; forming a gate structure over channel regions of the plurality of the fins; forming source/drain features over source/drain regions of the plurality of the fins; bonding the substrate on a carrier wafer; removing the first and second semiconductor layers to expose the dummy material; removing the dummy material in the trench; depositing a conductive material in the trench; and bonding the substrate to a silicon substrate such that the conductive material is in contact with the silicon substrate. The trench extends through the third semiconductor layer and has a bottom surface on the second semiconductor layer.

Abstract: Semiconductor structures and method for manufacturing the same are provided. The semiconductor structure includes a substrate and a first fin structure formed over the substrate. The semiconductor structure also includes an isolation structure formed around the first fin structure and a protection layer formed on the isolation structure. The semiconductor structure also includes first nanostructures formed over the first fin structure and a gate structure surrounding the first nanostructures. In addition, a bottom surface of the gate structure and the top surface of the isolation structure are separated by the protection layer.

Abstract: A semiconductor transistor device including a channel structure, gate structure, a first source/drain structure, a second source/drain structure, and a back-side source/drain contact. The gate structure overlies the channel structure. The first source/drain structure and the second source/drain structure are disposed on opposite endings of the channel structure. The back-side source/drain contact is disposed under the first source/drain structure. A line lies across the gate structure and the first source/drain structure. The line is parallel to an upper surface of the gate structure.

Abstract: A device includes a first stack of nanostructures formed over a substrate; a second stack of nanostructures formed adjacent to the first stack; a first gate structure on the nanostructures of the first stack; a second gate structure on the nanostructures of the second stack; a first insulating wall separating the first gate structure and the second gate structure; a hard mask layer on the first gate structure and on the second gate structure; and a gate contact extending through the hard mask layer to physically and electrically contact the first gate structure.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and an isolation structure between the first and second vertical structures. The isolation structure can include a center region and footing regions formed on opposite sides of the center region. Each of the footing regions can be tapered towards the center region from a first end of the each footing region to a second end of the each footing region.

Abstract: A method for manufacturing a semiconductor structure is provided. The method includes forming a plurality of fin structures extending along a first direction over a substrate, forming a low-k isolation strip over the substrate, the low-k isolation strip extending along the first direction and between the plurality of fin structures; and forming a high-k isolation strip on top of the low-k isolation strip.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.

Abstract: A method of forming a semiconductor device includes forming semiconductor strips protruding above a substrate and isolation regions between the semiconductor strips; forming hybrid fins on the isolation regions, the hybrid fins comprising dielectric fins and dielectric structures over the dielectric fins; forming a dummy gate structure over the semiconductor strip; forming source/drain regions over the semiconductor strips and on opposing sides of the dummy gate structure; forming nanowires under the dummy gate structure, where the nanowires are over and aligned with respective semiconductor strips, and the source/drain regions are at opposing ends of the nanowires, where the hybrid fins extend further from the substrate than the nanowires; after forming the nanowires, reducing widths of center portions of the hybrid fins while keeping widths of end portions of the hybrid fins unchanged, and forming an electrically conductive material around the nanowires.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a semiconductor fin having a first portion having a first width and a second portion having a second width substantially less than the first width. The first portion has a first surface, the second portion has a second surface, and the first and second surfaces are connected by a third surface. The third surface forms an angle with respect to the second surface, and the angle ranges from about 90 degrees to about 130 degrees. The structure further includes a gate electrode layer disposed over the semiconductor fin and source/drain epitaxial features disposed on the semiconductor fin on opposite sides of the gate electrode layer.

Abstract: A semiconductor structure includes a first stack of semiconductor layers disposed over a semiconductor substrate, where the first stack of semiconductor layers includes a first SiGe layer and a plurality of Si layers disposed over the first SiGe layer and the Si layers are substantially free of Ge, and a second stack of semiconductor layers disposed adjacent to the first stack of semiconductor layers, where the second stack of semiconductor layers includes the first SiGe layer and a plurality of second SiGe layers disposed over the first SiGe layer, and where the first SiGe layer and the second SiGe layers have different compositions. The semiconductor structure further includes a first metal gate stack interleaved with the first stack of semiconductor layers to form a first device and a second metal gate stack interleaved with the second stack of semiconductor layers to form a second device different from the first device.

Abstract: A method for manufacturing a semiconductor structure includes forming fins over a substrate. Each of the fins includes a base fin protruding from the substrate, and first semiconductor layers and second semiconductor layers alternating stacked over the base fin. The method further includes forming an isolation structure between the base fins, forming a hard mask layer over the isolation structure, and removing the second semiconductor layers, so that the first semiconductor layers and the hard mask layer are exposed in a gate trench. The method further includes forming a gate structure in the gate trench. The gate structure wraps around the first semiconductor layers and over the hard mask layer.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a first plurality of strip patterns and a second plurality of strip patterns that extend over an epitaxial stack in a first horizontal direction and are alternately arranged in a second horizontal direction perpendicular to the first horizontal direction. The method further includes patterning the first plurality of strip patterns to form a first plurality of island patterns, and patterning the second plurality of strip patterns to form a second plurality of island patterns. The first plurality of island patterns and the second plurality of island patterns are alternately arranged in the second horizontal direction. The method further includes etching the epitaxial stack using the first plurality of island patterns and second plurality of island patterns, thereby forming a fin structure.