Patents by Inventor Shi Ning Ju

Shi Ning Ju has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210226036
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an isolation structure formed over a substrate, and a first stacked nanostructure and a second stacked nanostructure extending above the isolation structure. The semiconductor device structure includes an inner spacer layer surrounding the first stacked nanostructure, and a dummy fin structure formed over the isolation structure. The dummy fin structure is between the first stacked nanostructure and the second stacked nanostructure, and a capping layer formed over the dummy fin structure. The inner spacer layer is in direct contact with the dummy fin structure and the capping layer.
    Type: Application
    Filed: April 1, 2021
    Publication date: July 22, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng CHING, Zhi-Chang LIN, Kuan-Ting PAN, Chih-Hao WANG, Shi-Ning JU
  • Publication number: 20210226037
    Abstract: A semiconductor device includes a first device fin and a second device fin. A first source/drain component is epitaxially grown over the first device fin. A second source/drain component is epitaxially grown over the second device fin. A first dummy fin structure is disposed between the first device fin and the second device fin. A gate structure partially wraps around the first device fin, the second device fin, and the first dummy fin structure. A first portion of the first dummy fin structure is disposed between the first source/drain component and the second source/drain component and outside the gate structure. A second portion of the first dummy fin structure is disposed underneath the gate structure. The first portion of the first dummy fin structure and the second portion of the first dummy fin structure have different physical characteristics.
    Type: Application
    Filed: April 5, 2021
    Publication date: July 22, 2021
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Shi Ning Ju, Kuan-Lun Cheng
  • Patent number: 11069793
    Abstract: A semiconductor device includes a plurality of nanostructures. The nanostructures each contain a semiconductive material. A plurality of first spacers circumferentially wrap around the nanostructures. A plurality of second spacers circumferentially wrap around the first spacers. A plurality of third spacers is disposed between the second spacers vertically. A gate structure surrounds the second spacers and the third spacers.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: July 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Shi Ning Ju, Kuan-Lun Cheng
  • Publication number: 20210202715
    Abstract: A semiconductor device includes a substrate, a first semiconductor fin, a second semiconductor fin, a gate structure, a plurality of source/drain structures, a shallow trench isolation (STI) oxide, and a dielectric layer. The first semiconductor fin extends upwardly from the substrate. The second semiconductor fin extends upwardly from the substrate. The gate structure extends across the first and second semiconductor fins. The source/drain structures are on the first and second semiconductor fins. The STI oxide extends continuously between the first and second semiconductor fins and has a U-shaped profile when viewed in a cross section taken along a lengthwise direction of the gate structure. The dielectric layer is partially embedded in the STI oxide and has a U-shaped profile when viewed in the cross section taken along the lengthwise direction of the gate structure.
    Type: Application
    Filed: March 12, 2021
    Publication date: July 1, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng CHING, Kuan-Lun CHENG, Chih-Hao WANG, Keng-Chu LIN, Shi-Ning JU
  • Publication number: 20210193531
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having self-aligned isolation structures. The present disclosure provides self-aligned isolation fins that can be formed by depositing dielectric material in openings formed in a spacing layer or by replacing portions of fins with dielectric material. The self-aligned isolation fins can be separated from each other by a critical dimension of the utilized photolithography process. The separation between self-aligned isolation fins or between the self-aligned isolation fins and active fins can be approximately equal to or larger than the separations of the active fins.
    Type: Application
    Filed: March 8, 2021
    Publication date: June 24, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng CHIANG, Chih-Hao Wang, Shi Ning Ju, Kuan-Lun Cheng, Kuan-Ting Pan
  • Publication number: 20210184015
    Abstract: FinFET patterning methods are disclosed for achieving fin width uniformity. An exemplary method includes forming a mandrel layer over a substrate. A first cut removes a portion of the mandrel layer, leaving a mandrel feature disposed directly adjacent to a dummy mandrel feature. The substrate is etched using the mandrel feature and the dummy mandrel feature as an etch mask, forming a dummy fin feature and an active fin feature separated by a first spacing along a first direction. A second cut removes a portion of the dummy fin feature and a portion of the active fin feature, forming dummy fins separated by a second spacing and active fins separated by the second spacing. The second spacing is along a second direction substantially perpendicular to the first direction. A third cut removes the dummy fins, forming fin openings, which are filled with a dielectric material to form dielectric fins.
    Type: Application
    Filed: February 9, 2021
    Publication date: June 17, 2021
    Inventors: Kuo-Cheng Ching, Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11038061
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure over a substrate, a first dielectric layer adjacent to the fin structure, and a second dielectric layer covering a sidewall of the first dielectric layer. The first dielectric layer has a different etching selectivity than the second dielectric layer. A bottom portion of the second dielectric layer is lower than a bottom surface of the first dielectric layer. The semiconductor device structure also includes a source/drain feature over the fin structure and covering a sidewall of the second dielectric layer, nanostructures over the fin structure, and a gate stack wrapping around the nanostructures.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: June 15, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Chiang, Shi-Ning Ju, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11038058
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a dielectric fin structure over the substrate. The semiconductor device structure also includes a semiconductor fin structure adjacent to the dielectric fin structure. The semiconductor device structure also includes a metal gate stack across the dielectric fin structure and the semiconductor fin structure. The semiconductor device structure also includes a source/drain feature over the semiconductor fin structure. The semiconductor device structure also includes a source/drain spacer interposed between the source/drain feature and the dielectric fin structure.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Chiang, Shi-Ning Ju, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20210175341
    Abstract: FinFET patterning methods are disclosed for achieving fin width uniformity. An exemplary method includes forming a mandrel layer over a substrate. A first cut removes a portion of the mandrel layer, leaving a mandrel feature disposed directly adjacent to a dummy mandrel feature. The substrate is etched using the mandrel feature and the dummy mandrel feature as an etch mask, forming a dummy fin feature and an active fin feature separated by a first spacing along a first direction. A second cut removes a portion of the dummy fin feature and a portion of the active fin feature, forming dummy fins separated by a second spacing and active fins separated by the second spacing. The second spacing is along a second direction substantially perpendicular to the first direction. A third cut removes the dummy fins, forming fin openings, which are filled with a dielectric material to form dielectric fins.
    Type: Application
    Filed: February 17, 2021
    Publication date: June 10, 2021
    Inventors: Kuo-Cheng Ching, Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11031292
    Abstract: A method of fabricating a device includes providing a first fin in a first device type region and a second fin in a second device type region. Each of the first and second fins include a plurality of semiconductor channel layers. A two-step recess of an STI region on opposing sides of each of the first and second fins is performed to expose a first number of semiconductor channel layers of the first fin and a second number of semiconductor channel layers of the second fin. A first gate structure is formed in the first device type region and a second gate structure is formed in the second device type region. The first gate structure is formed over the first fin having the first number of exposed semiconductor channel layers, and the second gate structure is formed over the second fin having the second number of exposed semiconductor channel layers.
    Type: Grant
    Filed: September 29, 2019
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shi Ning Ju, Kuo-Cheng Chiang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20210166947
    Abstract: A method of manufacturing a semiconductor device includes depositing a first material on a substrate, depositing on the substrate a second material that has an etch selectivity different from an etch selectively of the first material, depositing a spacer material on the first and second material, and etching the substrate using the spacer material as an etch mask to form a fin under the first material and a fin under the second material.
    Type: Application
    Filed: February 9, 2021
    Publication date: June 3, 2021
    Inventors: Lei-Chun Chou, Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Chin-Yuan Tseng, Hsin-Chih Chen, Shi Ning Ju, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Wei-Cheng Lin, Wei-Liang Lin
  • Publication number: 20210159311
    Abstract: Semiconductor structures and method for manufacturing the same are provided. The method for manufacturing the semiconductor structure includes forming a first fin structure including first semiconductor material layers and second semiconductor material layers alternately stacked over a substrate and forming an isolation structure surrounding the first fin structure. The method for manufacturing the semiconductor structure also includes forming a first capping layer over the isolation structure and covering a top surface and sidewalls of the first fin structure and etching the isolation structure to form a first gap between the first capping layer and a top surface of the isolation structure. The method for manufacturing the semiconductor structure also includes forming a protection layer covering a sidewall of the first capping layer and filling in the first gap.
    Type: Application
    Filed: November 27, 2019
    Publication date: May 27, 2021
    Inventors: Wen-Ting LAN, Guan-Lin CHEN, Shi-Ning JU, Kuo-Cheng CHIANG, Chih-Hao WANG, Ching-Wei TSAI, Kuan-Lun CHENG
  • Patent number: 11011427
    Abstract: A semiconductor layer is etched into a plurality of fin structures. A first nitridation process is performed to side surfaces of the fin structures. The first nitridation process forms a first oxynitride layer at the side surfaces of the fin structures. A liner oxide layer is formed on the first oxynitride layer. An isolation structure is formed around the fin structures after the forming of the liner oxide layer.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Shi Ning Ju, Chih-Hao Wang, Ying-Keung Leung, Carlos H. Diaz
  • Patent number: 11004960
    Abstract: A semiconductor device includes a substrate, a first dielectric fin, a second dielectric fin, a semiconductor fin, an epitaxy structure, and a metal gate structure. The first dielectric fin and the second dielectric fin disposed over the substrate. The semiconductor fin is disposed over the substrate, in which the semiconductor fin is between the first dielectric fin and the second dielectric fin. The epitaxy structure covers at least two surfaces of the semiconductor fin, in which the epitaxy structure is in contact with the first dielectric fin and is separated from the second dielectric fin. The metal gate structure crosses the first dielectric fin, the second dielectric fin, and the semiconductor fin.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: May 11, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Shi-Ning Ju, Kuan-Ting Pan, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11004959
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an isolation structure formed over a substrate, and a first stacked wire structure and a second stacked wire structure extending above the isolation structure. The semiconductor device structure includes a dummy fin structure formed over the isolation structure, and the dummy fin structure is between the first stacked wire structure and the second stacked wire structure. The semiconductor device structure also includes a capping layer formed over the dummy fin structure. The isolation structure has a first width, the dummy fin structure has a second width, and the second width is smaller than the first width.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Zhi-Chang Lin, Kuan-Ting Pan, Chih-Hao Wang, Shi-Ning Ju
  • Publication number: 20210135011
    Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes multiple semiconductor nanostructures over a substrate and two epitaxial structures over the substrate. Each of the semiconductor nanostructures is between the epitaxial structures, and the epitaxial structures are p-type doped. The semiconductor device structure also includes a gate stack wrapping around the semiconductor nanostructures. The semiconductor device structure further includes a dielectric stressor structure between the gate stack and the substrate. The epitaxial structures extend exceeding a top surface of the dielectric stressor structure.
    Type: Application
    Filed: March 30, 2020
    Publication date: May 6, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shi-Ning JU, Kuo-Cheng CHIANG, Guan-Lin CHEN, Chih-Hao WANG
  • Publication number: 20210134795
    Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor fin over a substrate and multiple semiconductor nanostructures suspended over the semiconductor fin. The semiconductor device structure also includes a gate stack extending across the semiconductor fin, and the gate stack wraps around each of the semiconductor nanostructures. The semiconductor device structure further includes a first epitaxial structure and a second epitaxial structure sandwiching the semiconductor nanostructures. Each of the first epitaxial structure and the second epitaxial structure extends exceeding a top surface of the semiconductor fin. In addition, the semiconductor device structure includes an isolation structure between the semiconductor fin and the gate stack. The isolation structure further extends exceeding opposite sidewalls of the first epitaxial structure.
    Type: Application
    Filed: May 11, 2020
    Publication date: May 6, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shi-Ning JU, Kuo-Cheng CHIANG, Kuan-Lun CHENG, Chih-Hao WANG
  • Publication number: 20210134721
    Abstract: Nanostructure field-effect transistors (nano-FETs) including isolation layers formed between epitaxial source/drain regions and semiconductor substrates and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a power rail, a dielectric layer over the power rail, a first channel region over the dielectric layer, a second channel region over the first channel region, a gate stack over the first channel region and the second channel region, where the gate stack is further disposed between the first channel region and the second channel region and a first source/drain region adjacent the gate stack and electrically connected to the power rail.
    Type: Application
    Filed: July 27, 2020
    Publication date: May 6, 2021
    Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Chih-Chao Chou, Wen-Ting Lan, Chih-Hao Wang
  • Publication number: 20210134798
    Abstract: In a method of manufacturing a semiconductor device, a separation wall made of a dielectric material is formed between two fin structures. A dummy gate structure is formed over the separation wall and the two fin structures. An interlayer dielectric (ILD) layer is formed over the dummy gate structure. An upper portion of the ILD layer is removed, thereby exposing the dummy gate structure. The dummy gate structure is replaced with a metal gate structure. A planarization operation is performed to expose the separation wall, thereby dividing the metal gate structure into a first gate structure and a second gate structure. The first gate structure and the second gate structure are separated by the separation wall.
    Type: Application
    Filed: December 14, 2020
    Publication date: May 6, 2021
    Inventors: Kuo-Cheng CHING, Chih-Hao WANG, Chih-Liang CHEN, Shi Ning JU
  • Publication number: 20210135008
    Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes multiple semiconductor nanostructures over a substrate and two epitaxial structures over the substrate. Each of the semiconductor nanostructures is between the epitaxial structures. The semiconductor device structure also includes a gate stack wrapping around the semiconductor nanostructures. The semiconductor device structure further includes a stressor structure between the gate stack and the substrate. The epitaxial structures extend exceeding a top surface of the stressor structure.
    Type: Application
    Filed: March 30, 2020
    Publication date: May 6, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng CHIANG, Shi-Ning JU, Guan-Lin CHEN, Chih-Hao WANG