Patents by Inventor Shi Ning Ju

Shi Ning Ju has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12148815
    Abstract: A fin field effect transistor device structure includes a substrate, an isolation structure, a first fin structure, a fin top layer, a first oxide layer, and a first gate structure. The first fin structure is disposed in the substrate and includes a base portion, a top portion, and a joint portion. The base portion is surrounded by the isolation structure. The top portion is exposed from the isolation structure. The joint portion connects the top portion and the base portion. The fin top layer is disposed over the top portion of the first fin structure. The fin top layer and the top portion of the first fin structure are made of different materials. The first oxide layer covers the fin top layer, the first fin structure, and the isolation structure. The first gate structure is disposed over the first oxide layer.
    Type: Grant
    Filed: June 30, 2023
    Date of Patent: November 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Kuan-Ting Pan, Shi-Ning Ju, Chih-Hao Wang
  • Publication number: 20240379878
    Abstract: A device includes a substrate, a first semiconductor channel over the substrate, a second semiconductor channel over the substrate and laterally offset from the first semiconductor channel, and a third semiconductor channel over the substrate and laterally offset from the second semiconductor channel. A first gate structure, a second gate structure, and a third gate structure are over and lateral surround the first, second, and third semiconductor channels, respectively. A first inactive fin is between the first gate structure and the second gate structure, and a second inactive fin is between the second gate structure and the third gate structure. A bridge conductor layer is over the first, second, and third gate structures, and the first and second inactive fins. A dielectric plug extends from an upper surface of the second inactive fin, through the bridge conductor layer, to at least an upper surface of the bridge conductor layer.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Shi-Ning JU, Kuo-Cheng CHIANG, Chih-Hao WANG, Kuan-Lun CHENG, Guan-Lin CHEN, Kuan-Ting PAN
  • Publication number: 20240379668
    Abstract: Semiconductor devices and method of forming the same are provided. In one embodiment, a semiconductor device includes a first transistor and a second transistor. The first transistor includes two first source/drain features and a first number of nanostructures that are stacked vertically one over another and extend lengthwise between the two first source/drain features. The second transistor includes two second source/drain features and a second number of nanostructures that are stacked vertically one over another and extend lengthwise between the two second source/drain features.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Jung-Chien Cheng, Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Chih-Hao Wang, Kuan-Lun Cheng
  • Publication number: 20240379750
    Abstract: A method of forming a semiconductor device includes: forming a fin structure protruding above a substrate, where the fin structure comprises a fin and a layer stack overlying the fin, where the layer stack comprises alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin structure; forming openings in the fin structure on opposing sides of the dummy gate structure, where the openings extend through the layer stack into the fin; forming a dielectric layer in bottom portions of the openings; and forming source/drain regions in the openings on the dielectric layer, where the source/drain regions are separated from the fin by the dielectric layer.
    Type: Application
    Filed: July 17, 2024
    Publication date: November 14, 2024
    Inventors: Guan-Lin Chen, Kuo-Cheng Chiang, Shi Ning Ju, Jung-Chien Cheng, Chih-Hao Wang, Kuan-Lun Cheng
  • Patent number: 12142692
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes multiple first semiconductor nanostructures suspended over a substrate and multiple second semiconductor nanostructures suspended over the substrate. The semiconductor device structure also includes a dielectric fin between the first semiconductor nanostructures and the second semiconductor nanostructures. The semiconductor device structure further includes a metal gate stack wrapped around the dielectric fin, the first semiconductor nanostructures and the second semiconductor nanostructures. The metal gate stack has a gate dielectric layer and a gate electrode, and the gate dielectric layer extends along a sidewall and a topmost surface of the dielectric fin.
    Type: Grant
    Filed: July 13, 2023
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Chiang, Huan-Chieh Su, Kuan-Ting Pan, Shi-Ning Ju, Chih-Hao Wang
  • Publication number: 20240371934
    Abstract: Semiconductor structures and method for manufacturing the same are provided. The semiconductor structure includes a substrate and a first fin structure formed over the substrate. The semiconductor structure also includes an isolation structure formed around the first fin structure and a protection layer formed on the isolation structure. The semiconductor structure also includes first nanostructures formed over the first fin structure and a gate structure surrounding the first nanostructures. In addition, a bottom surface of the gate structure and the top surface of the isolation structure are separated by the protection layer.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Inventors: Wen-Ting LAN, Guan-Lin CHEN, Shi-Ning JU, Kuo-Cheng CHIANG, Chih-Hao WANG, Ching-Wei TSAI, Kuan-Lun CHENG
  • Publication number: 20240371877
    Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure includes first channel members vertically stacked, second channel members vertically stacked, a first source/drain feature abutting the first channel members, a second source/drain feature abutting the second channel members, a first gate structure engaging the first channel members, a second gate structure engaging the second channel members, a first metal interconnect layer disposed at a frontside of the semiconductor device, and a second metal interconnect layer disposed at a backside of the semiconductor device. The first and second gate structures are stacked vertically between the first and second metal interconnect layers. The exemplary semiconductor structure also includes an isolation structure stacked vertically between the first and second metal interconnect layers. The isolation structure includes an air gap stacked laterally between the first and second gate structures.
    Type: Application
    Filed: July 17, 2024
    Publication date: November 7, 2024
    Inventors: Jung-Chien Cheng, Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Chih-Hao Wang, Kuan-Lun Cheng
  • Publication number: 20240371866
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes first nanostructures and second nanostructures stacked in a vertical direction over a substrate, and a first dielectric structure between the first nanostructures and the second nanostructures. The semiconductor device structure includes a first gate structure formed over the first nanostructures. The first gate structure comprises a gate dielectric layer, and a topmost surface of the gate dielectric layer is higher than a top surface of the first dielectric structure.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng CHIANG, Shi-Ning JU, Chih-Hao WANG, Kuan-Ting PAN, Zhi-Chang LIN
  • Publication number: 20240371692
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. The semiconductor structure also includes a gate structure wrapping around the nanostructures and a first dielectric feature separating the gate structure into a first portion and a second portion. The semiconductor structure also includes a metal layer formed over the gate structure. In addition, top surfaces of the first portion and the second portion of the gate structure and a top surface of the first dielectric feature are covered by the metal layer.
    Type: Application
    Filed: July 11, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jia-Chuan YOU, Chia-Hao CHANG, Kuan-Ting PAN, Shi-Ning JU, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20240363630
    Abstract: Gate isolation techniques disclosed herein form gate isolation fins to isolate metal gates of multigate devices from one another before forming the multigate devices, and in particular, before forming the metal gates of the multigate devices. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A gate isolation fin, which separates the first metal gate and the second metal gate, includes a dielectric feature having a first dielectric layer having a first dielectric constant (e.g., a low-k dielectric core) and a second dielectric layer (e.g., a high-k dielectric shell) surrounding the first dielectric layer. The second dielectric layer has a second dielectric constant that is greater than the first dielectric constant.
    Type: Application
    Filed: July 11, 2024
    Publication date: October 31, 2024
    Inventors: Kuan-Ting PAN, Kuo-Cheng CHIANG, Shi Ning JU, Yi-Ruei JHAN, Kuan-Lun CHENG, Chih-Hao WANG
  • Publication number: 20240363522
    Abstract: Semiconductor devices and methods are provided. A method according to the present disclosure includes receiving a substrate that includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; forming a plurality of fins over the third semiconductor layer; forming a trench between two of the plurality of fins; depositing a dummy material in the trench; forming a gate structure over channel regions of the plurality of the fins; forming source/drain features over source/drain regions of the plurality of the fins; bonding the substrate on a carrier wafer; removing the first and second semiconductor layers to expose the dummy material; removing the dummy material in the trench; depositing a conductive material in the trench; and bonding the substrate to a silicon substrate such that the conductive material is in contact with the silicon substrate. The trench extends through the third semiconductor layer and has a bottom surface on the second semiconductor layer.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Inventors: Chih-Chao Chou, Kuo-Cheng Chiang, Shi Ning Ju, Wen-Ting Lan, Chih-Hao Wang
  • Patent number: 12132115
    Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes multiple semiconductor nanostructures over a substrate and two epitaxial structures over the substrate. Each of the semiconductor nanostructures is between the epitaxial structures, and the epitaxial structures are p-type doped. The semiconductor device structure also includes a gate stack wrapping around the semiconductor nanostructures. The semiconductor device structure further includes a dielectric stressor structure between the gate stack and the substrate. The epitaxial structures extend exceeding a top surface of the dielectric stressor structure.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: October 29, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shi-Ning Ju, Kuo-Cheng Chiang, Guan-Lin Chen, Chih-Hao Wang
  • Publication number: 20240355904
    Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The method includes depositing a spacer layer over an isolation region between adjacent fin structures, and the spacer layer is formed on sidewalls and tops of the fin structures. The method further includes forming a mask on the spacer layer between the fin structures, and the mask has a height substantially less than a height of the fin structures. The method further includes removing portions of the spacer layer and recessing the fin structures to form a spacer and to expose a portion of each fin structure, the spacer includes a first portion having a ā€œUā€ shape disposed on the isolation region, and the portion of each fin structure has a top surface located at a level substantially below a top surface of the isolation region. The method further includes removing the mask.
    Type: Application
    Filed: August 16, 2023
    Publication date: October 24, 2024
    Inventors: Jung-Chien CHENG, Guan-Lin CHEN, Shi Ning JU, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Patent number: 12125877
    Abstract: A method of forming a semiconductor device includes: forming a fin structure protruding above a substrate, where the fin structure comprises a fin and a layer stack overlying the fin, where the layer stack comprises alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin structure; forming openings in the fin structure on opposing sides of the dummy gate structure, where the openings extend through the layer stack into the fin; forming a dielectric layer in bottom portions of the openings; and forming source/drain regions in the openings on the dielectric layer, where the source/drain regions are separated from the fin by the dielectric layer.
    Type: Grant
    Filed: April 25, 2023
    Date of Patent: October 22, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Guan-Lin Chen, Kuo-Cheng Chiang, Shi Ning Ju, Jung-Chien Cheng, Chih-Hao Wang, Kuan-Lun Cheng
  • Publication number: 20240347591
    Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes first nanostructures formed over a substrate, and a first gate electrode layer formed on the first nanostructures. The semiconductor structure includes a second gate electrode layer adjacent to the first gate electrode layer, and a protective layer formed over the first gate electrode layer and the second gate electrode layer. The semiconductor structure includes a first dielectric structure between the first gate electrode layer and the second gate electrode layer, and the first dielectric structure penetrates through the protective layer.
    Type: Application
    Filed: April 12, 2023
    Publication date: October 17, 2024
    Inventors: Kuo-Cheng CHIANG, Guan-Lin CHEN, Jung-Chien CHENG, Shi-Ning JU, Chih-Hao WANG
  • Publication number: 20240347391
    Abstract: Self-aligned gate cutting techniques for multigate devices are disclosed herein that provide multigate devices having asymmetric metal gate profiles and asymmetric source/drain feature profiles. An exemplary multigate device has a channel layer, a metal gate that wraps a portion of the channel layer, and source/drain features disposed over a substrate. The channel layer extends along a first direction between the source/drain features. A first dielectric fin and a second dielectric fin are disposed over the substrate and configured differently. The channel layer extends along a second direction between the first dielectric fin and the second dielectric fin. The metal gate is disposed between the channel layer and the second dielectric fin. In some embodiments, the first dielectric fin is disposed on a first isolation feature, and the second dielectric fin is disposed on a second isolation feature. The first isolation feature and the second isolation feature are configured differently.
    Type: Application
    Filed: June 24, 2024
    Publication date: October 17, 2024
    Inventors: Guan-Lin Chen, Chih-Hao Wang, Ching-Wei Tsai, Shi Ning Ju, Jui-Chien Huang, Kuo-Cheng Chiang, Kuan-Lun Cheng
  • Publication number: 20240347535
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first substrate fin and a second substrate fin extending in a first direction, a first isolation strip extending in the first direction and spaced apart from the first substrate fin and the second substrate fin, a first source/drain structure on the first substrate fin, and a second source/drain structure on the second substrate fin. The first isolation strip is sandwiched between and in contact with a first sidewall of the first source/drain structure and a first sidewall of the second source/drain structure.
    Type: Application
    Filed: June 25, 2024
    Publication date: October 17, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shi Ning JU, Kuo-Cheng CHIANG, Kuan-Lun CHENG, Chih-Hao WANG, Kuan-Ting PAN, Zhi-Chang LIN
  • Publication number: 20240339526
    Abstract: A semiconductor structure includes a plurality of fin structures extending along a first direction, a plurality of gate structure segments positioned along a line extending in a second direction, the second direction being orthogonal to the first direction, wherein the gate structure segments are separated by dummy fin structures. The semiconductor structure further includes a conductive layer disposed over both the gate structure segments and the dummy fin structures to electrically connect at least some of the gate structure segments, and a cut feature aligned with one of the dummy fin structures and positioned to electrically isolate gate structure segments on both sides of the one of the dummy fin structures.
    Type: Application
    Filed: June 21, 2024
    Publication date: October 10, 2024
    Inventors: Kuan-Ting Pan, Huan-Chieh Su, Jia-Chuan You, Shi Ning Ju, Kuo-Cheng Chiang, Yi-Ruei Jhan, Li-Yang Chuang, Chih-Hao Wang
  • Publication number: 20240339455
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a semiconductor fin having a first portion having a first width and a second portion having a second width substantially less than the first width. The first portion has a first surface, the second portion has a second surface, and the first and second surfaces are connected by a third surface. The third surface forms an angle with respect to the second surface, and the angle ranges from about 90 degrees to about 130 degrees. The structure further includes a gate electrode layer disposed over the semiconductor fin and source/drain epitaxial features disposed on the semiconductor fin on opposite sides of the gate electrode layer.
    Type: Application
    Filed: June 17, 2024
    Publication date: October 10, 2024
    Inventors: Wen-Ting LAN, Chih-Hao WANG, Shi Ning JU, Kuo-Cheng CHIANG, Kuan-Lun CHENG
  • Publication number: 20240339531
    Abstract: A semiconductor device according to the present disclosure includes a first base fin and a second base fin extending from a substrate, an isolation feature disposed between the first base fin and the second base fin, a first dummy epitaxial layer disposed on the first base fin, a second dummy epitaxial layer disposed on the second base fin, a first insulator layer over the first dummy epitaxial layer, a second insulator layer over the second dummy epitaxial layer, a first source/drain feature disposed on the first insulator layer, a second source/drain feature disposed on the second insulator layer. A thickness of the first dummy epitaxial layer measured from a top surface of the first base fin is smaller than a thickness of the second dummy epitaxial layer measured from a top surface of the second base fin.
    Type: Application
    Filed: August 4, 2023
    Publication date: October 10, 2024
    Inventors: Guan-Lin Chen, Kuo-Cheng Chiang, Shi Ning Ju, Jung-Chien Cheng, Chih-Hao Wang