Patents by Inventor Shi-Yul Kim
Shi-Yul Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7923176Abstract: A mask includes a transparent substrate, a light-blocking layer and a halftone layer. The light-blocking layer includes a source electrode pattern portion including a first electrode portion, a second electrode portion and a third electrode portion, and a drain electrode pattern portion disposed between the second electrode portion and the third electrode portion. The halftone layer includes a halftone portion corresponding to a spaced-apart portion between the source electrode pattern portion and the drain electrode pattern portion, and a dummy halftone portion more protrusive than ends of the second electrode portion and the third electrode portion. Thus, a photoresist pattern corresponding to a channel portion of a thin film transistor (TFT) may be formed with a uniform thickness, to thereby prevent an excessive etching of the channel portion.Type: GrantFiled: February 21, 2008Date of Patent: April 12, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Chong-Chul Chai, Mee-Hye Jung, Woo-Geun Lee, Woo-Seok Jeon, Young-Wook Lee, Jung-In Park, Jun-Hyung Souk, Won-Kie Chang, Shi-Yul Kim
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Publication number: 20110051059Abstract: An organic layer composition and a liquid crystal display including the same are provided. An organic layer composition according to an exemplary embodiment includes a binder formed by copolymerizing compounds included in a first group and a second group, wherein the first group includes an acryl-based compound and the second group includes a compound without a —COO— group.Type: ApplicationFiled: March 12, 2010Publication date: March 3, 2011Inventors: Hoon Kang, Jae-Sung Kim, Yang-Ho Jung, Jin-Ho Ju, Doo-Hee Jung, Jung-In Park, Shi-Yul Kim
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Patent number: 7888675Abstract: The present invention provides a manufacturing method of a thin film transistor array panel, which includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact on the gate line; forming a first conducting film including Mo, a second conducting film including Al, and a third conducting film including Mo on the ohmic contact; forming a first photoresist pattern on the third conducting film; etching the first, second, and third conducting films, the ohmic contact, and the semiconductor layer using the first photoresist pattern as a mask; removing the first photoresist pattern by a predetermined thickness to form a second photoresist pattern; etching the first, second, and third conducting films using the second photoresist pattern as a mask to expose a portion of the ohmic contact; and etching the exposed ohmic contact using a Cl-containing gas and a F-containing gas.Type: GrantFiled: April 8, 2008Date of Patent: February 15, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Gab Kim, Woo-Geun Lee, Shi-Yul Kim, Jin-Ho Ju, Jang-Soo Kim, Sang-Woo Whangbo, Min-Seok Oh, Hye-Young Ryu, Hong-Kee Chin
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Patent number: 7876412Abstract: A method for manufacturing a TFT array panel including forming a gate line having a gate electrode on a insulating layer, a gate insulating layer on the gate line, a semiconductor on the gate insulating layer, an ohmic contact on the semiconductor, a data line having a source electrode and a drain electrode apart form the source electrode on the ohmic contact, a passivation layer having a contact hole to expose the drain electrode, and a pixel electrode connected to the drain electrode through the contact hole. The drain electrode and the source electrode are formed by a photolithography using a negative photoresist pattern. The negative photoresist pattern includes a first portion having a first thickness corresponding to a channel area, a second portion having a second thickness corresponding to a data line area, and a third portion having a third thickness corresponding to another area.Type: GrantFiled: February 11, 2010Date of Patent: January 25, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Gab Kim, Min-Seok Oh, Hong-Kee Chin, Jeong-Min Park, Shi-Yul Kim, Hee-Hwan Choe
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Patent number: 7846618Abstract: A multi-tone optical mask includes a substrate, a light-blocking pattern, a first semi-transmitting pattern and a second semi-transmitting pattern. The light-blocking pattern is formed on the substrate. The first semi-transmitting pattern is formed on the substrate. The second semi-transmitting pattern partially overlaps the first semi-transmitting pattern. The multi-tone optical mask has at least five different light-transmittances corresponding to a plurality of areas divided on the substrate.Type: GrantFiled: April 5, 2007Date of Patent: December 7, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Chong-Chul Chai, Soo-Wan Yoon, Shi-Yul Kim, Joo-Ae Youn
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Publication number: 20100291722Abstract: An etchant includes about 0.1 percent by weight to about 30 percent by weight of ammonium persulfate (NH4)2S2O8, about 0.1 percent by weight to about 10 percent by weight of an inorganic acid, about 0.1 percent by weight to about 10 percent by weight of an acetate salt, about 0.01 percent by weight to about 5 percent by weight of a fluorine-containing compound, about 0.01 percent by weight to about 5 percent by weight of a sulfonic acid compound, about 0.01 percent by weight to about 2 percent by weight of an azole compound, and a remainder of water. Accordingly, the etchant may have high stability to maintain etching ability. Thus, manufacturing margins may be improved so that manufacturing costs may be reduced.Type: ApplicationFiled: May 11, 2010Publication date: November 18, 2010Inventors: Bong-Kyun Kim, Jong-Hyun Choung, Byeong-Jin Lee, Sun-Young Hong, Hong-Sick Park, Shi-Yul Kim, Ki-Beom Lee, Sam-Young Cho, Sang-Woo Kim, Hyun-Cheol Shin, Won-Guk Seo
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Publication number: 20100270554Abstract: A method of reforming a metal pattern for improving the productivity and reliability of a manufacturing process, an array substrate and a method of manufacturing the array substrate are disclosed. In the method, a first wiring pattern is formed on an insulation substrate. The first wiring pattern is removed. A second wiring pattern is formed on an embossed pattern by using the embossed pattern as an alignment mask. The embossed pattern is defined by a recess formed on a surface of the insulation substrate. Accordingly, the insulation substrate having the recess formed thereon may not be discarded, and may be reused in forming the first wiring pattern. In addition, the embossed pattern defined by the recess is used as an alignment mask, so that the alignment reliability of a metal pattern may be improved.Type: ApplicationFiled: November 24, 2009Publication date: October 28, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun-Young HONG, Hong-Sick Park, Shi-Yul Kim, Bong-Kyun Kim, Young-Joo Choi, Byeong-Jin Lee, Jong-Hyun Choung, Dong-Ju Yang, Hyun-Young Jung
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Patent number: 7820368Abstract: A photoresist stripper composition, a method for forming wire structures thereby, and a method of fabricating a thin film transistor substrate using the composition. The photoresist stripper composition includes about 50 WT % to about 70 WT % of butyldiglycol, about 20 to about 40 WT % of an alkylpyrrolidone, about 1 WT % to about 10 WT % of an organic amine compound, about 1 to about 5 WT % of aminopropylmorpholine, and about 0.01 to about 0.5 WT % of a mercapto compound.Type: GrantFiled: July 25, 2006Date of Patent: October 26, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Hong-sick Park, Shi-yul Kim, Jong-hyun Choung, Won-suk Shin
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Publication number: 20100261322Abstract: A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.Type: ApplicationFiled: June 9, 2010Publication date: October 14, 2010Inventors: Jang-Soo Kim, Hong-Long Ning, Bong-Kyun Kim, Hong-Sick Park, Shi-Yul Kim, Chang-Oh Jeong, Sang-Gab Kim, Jae-Hyoung Youn, Woo-Geun Lee, Yang-Ho Bae, Pil-Sang Yun, Jong-Hyun Choung, Sun-Young Hong, Ki-Won Kim, Byeong-Jin Lee, Young-Wook Lee, Jong-In Kim, Byeong-Beom Kim, Nam-Seok Suh
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Patent number: 7804093Abstract: A thin film transistor array panel includes an insulating substrate, a gate line and a data line disposed on the insulating substrate and insulated from and intersecting each other, a thin film transistor connected to the gate line and the data line, a partition disposed corresponding to the gate line and the data line and defining a color filter filling region, a color filter disposed in the filling region, a passivation layer disposed on the color filter and the partition, and a pixel electrode disposed on the passivation layer and connected to the thin film transistor through a contact hole disposed through the passivation layer and the color filter. A plane shape of the color filter filling region is substantially a rectangle.Type: GrantFiled: December 16, 2008Date of Patent: September 28, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jang-Soo Kim, Sang-Soo Kim, Shi-Yul Kim, Jang-Sub Kim
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Patent number: 7795685Abstract: A method of manufacturing a thin film transistor substrate includes forming a transistor thin layer pattern, forming a protecting layer, forming a photoresist film, forming a pixel electrode and a conductive layer that are separated from each other, stripping a photoresist pattern to remove the conductive layer using a stripping composition and dissolving the conductive layer. The method of manufacturing a thin film transistor substrate is capable of improving an efficiency of manufacturing process of the thin film transistor substrate. In addition, the stripping composition is recycled.Type: GrantFiled: October 19, 2007Date of Patent: September 14, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Hong-Sik Park, Shi-Yul Kim, Jong-Hyun Choung, Won-Suk Shin
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Publication number: 20100203715Abstract: The present invention provides a manufacturing method of a thin film transistor array panel, which includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact on the gate line; forming a first conducting film including Mo, a second conducting film including Al, and a third conducting film including Mo on the ohmic contact; forming a first photoresist pattern on the third conducting film; etching the first, second, and third conducting films, the ohmic contact, and the semiconductor layer using the first photoresist pattern as a mask; removing the first photoresist pattern by a predetermined thickness to form a second photoresist pattern; etching the first, second, and third conducting films using the second photoresist pattern as a mask to expose a portion of the ohmic contact; and etching the exposed ohmic contact using a Cl-containing gas and a F-containing gas.Type: ApplicationFiled: April 22, 2010Publication date: August 12, 2010Inventors: Sang-Gab KIM, Woo-Geun Lee, Shi-Yul Kim, Jin-Ho Ju, Jang-Soo Kim, Sang-Woo Whangbo, Min-Seok Oh, Hye-Young Ryu, Hong-Kee Chin
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Patent number: 7759738Abstract: A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.Type: GrantFiled: November 12, 2008Date of Patent: July 20, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jang-Soo Kim, Hong-Long Ning, Bong-Kyun Kim, Hong-Sick Park, Shi-Yul Kim, Chang-Oh Jeong, Sang-Gab Kim, Jae-Hyoung Youn, Woo-Geun Lee, Yang-Ho Bae, Pil-Sang Yun, Jong-Hyun Choung, Sun-Young Hong, Ki-Won Kim, Byeong-Jin Lee, Young-Wook Lee, Jong-In Kim, Byeong-Beom Kim, Nam-Seok Suh
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Publication number: 20100140626Abstract: A method for manufacturing a TFT array panel including forming a gate line having a gate electrode on a insulating layer, a gate insulating layer on the gate line, a semiconductor on the gate insulating layer, an ohmic contact on the semiconductor, a data line having a source electrode and a drain electrode apart form the source electrode on the ohmic contact, a passivation layer having a contact hole to expose the drain electrode, and a pixel electrode connected to the drain electrode through the contact hole. The drain electrode and the source electrode are formed by a photolithography using a negative photoresist pattern. The negative photoresist pattern includes a first portion having a first thickness corresponding to a channel area, a second portion having a second thickness corresponding to a data line area, and a third portion having a third thickness corresponding to another area.Type: ApplicationFiled: February 11, 2010Publication date: June 10, 2010Inventors: Sang-Gab Kim, Min-Seok Oh, Hong-Kee Chin, Jeong-Min Park, Shi-Yul Kim, Hee-Hwan Choe
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Patent number: 7695779Abstract: An organic composition having liquid-crystal alignment characteristics includes a photosensitive compound and a binder resin represented by Formula 1 below: wherein each R1 is independently hydrogen or a methyl group; R2 is an alkyl group of 4-16 carbon atoms; R3 is an alkyl group of 1-7 carbon atoms, a cyclooxyalkyl group of 1-7 carbon atoms, a benzyl group, or a phenyl group; l, m, and n represent molar ratios of polymerization units and are respectively from about 0.01 to about 0.50, from about 0.10 to about 0.60, and from about 0.03 to about 0.50.Type: GrantFiled: April 14, 2006Date of Patent: April 13, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-ho Ju, Dong-ki Lee, Hi-kuk Lee, Shi-yul Kim, Jae-ho Lee
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Patent number: 7688417Abstract: A method for manufacturing a TFT array panel including forming a gate line having a gate electrode on a insulating layer, a gate insulating layer on the gate line, a semiconductor on the gate insulating layer, an ohmic contact on the semiconductor, a data line having a source electrode and a drain electrode apart form the source electrode on the ohmic contact, a passivation layer having a contact hole to expose the drain electrode, and a pixel electrode connected to the drain electrode through the contact hole. The drain electrode and the source electrode are formed by a photolithography using a negative photoresist pattern. The negative photoresist pattern includes a first portion having a first thickness corresponding to a channel area, a second portion having a second thickness corresponding to a data line area, and a third portion having a third thickness corresponding to another area.Type: GrantFiled: October 21, 2005Date of Patent: March 30, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Gab Kim, Min-Seok Oh, Hong-Kee Chin, Jeong-Min Park, Shi-Yul Kim, Hee-Hwan Choe
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Publication number: 20100065848Abstract: Provided are a thin-film transistor (TFT) substrate which can facilitate the formation of contact holes and has improved reliability and a method of fabricating the TFT substrate. The TFT substrate includes a gate wiring formed on an insulating substrate; a data wiring defining a pixel region by intersecting the gate wiring, the data wiring including a source electrode and a drain electrode; a plurality of black matrix barrier ribs formed along the boundaries of the pixel region; a color filter formed to cover the pixel region; a pixel electrode formed on the color filter; and a plurality of contact holes formed through the color filter near the corners of the pixel region through which the pixel electrode and the drain electrode contact each other.Type: ApplicationFiled: May 19, 2009Publication date: March 18, 2010Inventors: Eun-Guk LEE, Jang-Soo KIM, Hyang-Shik KONG, Sang-Soo KIM, Shi-Yul KIM, Yoon-Ho KANG, Hoon KANG, Byung-Duk YANG, Kyoung-Tai KIM, Dong-Yoon KIM
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Publication number: 20100053507Abstract: After increasing the thickness of a gate line and forming a barrier rib that is made of an organic material, a gate insulating layer is formed and then a color filter is formed with an Inkjet method using the barrier rib. By increasing a thickness of the gate line, even if the size of a substrate increases, problems due to signal delay are reduced, and by forming a barrier rib with an organic material, the height of the barrier rib increases, and a taper angle increases and thus a color filter is stably formed.Type: ApplicationFiled: May 4, 2009Publication date: March 4, 2010Applicant: Samsung Electronics Co., Ltd.Inventors: Jean-Ho SONG, Yang-Ho JUNG, Hoon KANG, Jae-Sung KIM, Jae-Hyoung YOUN, Jong-In KIM, Sang-Soo KIM, Shi-Yul KIM
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Publication number: 20100051951Abstract: A thin film transistor (“TFT”) array panel includes; an insulation substrate, a TFT disposed on the insulation substrate and including a drain electrode, a passivation layer covering the TFT and including a contact portion disposed therein corresponding to the drain electrode, a partition comprising an organic material disposed on the passivation layer, and including a transverse portion, a longitudinal portion, and a contact portion disposed on the drain electrode, a color filter disposed on the passivation layer and disposed in a region defined by the partition, an organic capping layer disposed on the partition and the color filter, and a pixel electrode disposed on the organic capping layer, and connected to the drain electrode through the contact portion of the passivation layer and the contact portion of the partition, wherein a contact hole is formed in the organic capping layer corresponding to the contact portion of the passivation layer.Type: ApplicationFiled: March 31, 2009Publication date: March 4, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwang-Ho Lee, Jang-Soo Kim, Hong-Suk Yoo, Sang-Soo Kim, Shi-Yul Kim, Jae-Hyoung Youn
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Patent number: 7662676Abstract: A thin film transistor (TFT) array panel with signal lines that have low resistivity is presented. The TFT array panel includes an insulating substrate, a gate line formed on the insulating substrate, a gate insulating layer formed on the gate line, a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode facing the source electrode with a gap, and a pixel electrode connected to the drain electrode. In one embodiment, at least one of the gate line, the data line, and the drain electrode includes a first conductive layer made of a Mo-containing conductor, a second conductive layer made of a Cu-containing conductor, and a third conductive layer made of a MoN-containing conductor.Type: GrantFiled: November 12, 2008Date of Patent: February 16, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Hong-Sick Park, Shi-Yul Kim