Abstract: A method for fabricating a semiconductor device with high-k materials. A high-k dielectric layer is formed on a substrate, followed by a fluorine-containing treatment of the high-k dielectric layer, forming an interface containing Si—F bonds.

Abstract: A method of fabricating a MOS transistor by millisecond annealing. A semiconductor substrate with a gate stack comprising a gate electrode overlying a gate dielectric layer on a top surface of a semiconductor substrate is provided. At least one implanting process is performed to form two doped regions on opposite sides of the gate electrode. Millisecond annealing activates dopants in the doped regions. The millisecond anneal includes rapid heating and rapid cooling within 1 to 50 milliseconds.

Abstract: A novel metal gate structure includes a gate oxide layer formed on a surface of a silicon substrate, a doped silicon layer stacked on the gate oxide layer, a CVD ultra-thin titanium nitride film deposited on the doped silicon layer, a tungsten nitride layer stacked on the CVD ultra-thin titanium nitride film, a tungsten layer stacked on the tungsten nitride layer, and a nitride cap layer stacked on the tungsten layer. A liquid phase deposition (LPD) oxide spacer is formed on each sidewall of the metal gate stack. A silicon nitride spacer is formed on the LPD oxide spacer. The thickness of the CVD ultra-thin titanium nitride film is between 10 and 100 angstroms.

Abstract: An ion beam energy monitor system and method thereof. A physical field generator generates a physical field in a direction not parallel to an ion beam, refracting the ion beam, and a receiving device located on the path of the refracted ion beam receives the ion beam and calculates the energy thereof according to a collision distribution of ions of the ion beam. The output energy of the ion beam is thus being well adjusted.

Abstract: The present invention discloses a method and a device of monitoring an ion beam energy distribution by applying various voltages onto a conductive plate having an opening to generate various electric fields on the path passed by the ion beam so as to control the ion beam passing through said opening, and measuring the current created by the passing ion beam. The obtained relation between the applied voltages and the ion beam current therefore indicates the energy distribution of said ion beam. Furthermore, a step of adjusting the ion beam parameters in accordance with the measured relation between the voltages and current mentioned above can be performed, and the monitoring and adjusting steps can be repeated until the expected ion beam energy distribution is obtained, so that the purity/accuracy of the ion beam energy is improved.

Abstract: A method of forming a silicon nitride layer. The method comprises providing a substrate having a silicon surface thereon, performing an ion implant process on the silicon surface, implanting nitrogen atoms into the silicon surface, and performing a thermal nitridation process and forming a silicon nitride layer on the substrate, wherein the silicon nitride layer comprises the silicon nitride formed on the silicon surface by reaction of the silicon surface with the nitrogen atoms contained therein.

Abstract: Afin-type trench capacitor structure includes a buried plate diffused into a silicon substrate. The buried plate, which surrounds a bottle-shaped lower portion of the trench capacitor structure, is electrically connected to an upwardly extending annular poly electrode, thereby enabling the buried plate and the annular poly electrode to constitute a large-area capacitor electrode of the trench capacitor structure. A capacitor storage node consisting of a surrounding conductive layer, a central conductive layer and a collar conductive layer encompasses the upwardly extending annular poly electrode. A first capacitor dielectric layer isolates the capacitor storage node from the buried plate. A second capacitor dielectric layer and a third capacitor dielectric layer isolate the upwardly extending annular poly electrode from the capacitor storage node.

Abstract: A method for forming a bottle trench. First, a substrate covered by a photoresist layer is rotated to a specific angle prior to performance of lithography, thereby forming a rectangular opening in the photoresist layer and exposing the substrate, in which edges of the rectangular opening are substantially parallel to the {110} plane of the substrate due to the rotation of the substrate. Next, the exposed substrate is etched to form a trench therein, in which the sidewall surface of the trench is the {110} plane of the substrate. Finally, isotropic etching is performed on the substrate of the lower portion of the trench using an etching shield layer formed on the sidewall of the upper portion of the trench as an etching mask, to form the bottle trench. The invention also discloses a method of fabricating a bottle trench capacitor.

Abstract: A method for forming a deep trench capacitor mainly utilizes a liquid phase deposition (LPD) oxide to form a collar oxide layer in the trench, followed by forming a conductive layer serving as an upper electrode of the deep trench capacitor, thereby avoiding collar oxide residue in the conductive layer and thus forming good electrical connection. And, the method of the present invention does not need a dry etch to remove the unnecessary collar oxide layer such that the process can be simplified.

Abstract: A method for forming a self-aligned contact on a semiconductor substrate provided with a plurality of field-effect transistors. The method comprises the steps of forming a first insulating layer comprising a nitride along a profile of a gate structure and a junction region, forming a temporary layer comprising a doped oxide on the first insulating layer, removing a portion of the temporary layer by performing a selective etch of the oxide with a mask while leaving a plug portion of the temporary layer over the junction region, forming a second insulating layer comprising an undoped oxide in a region where the portion of the temporary layer is removed, removing the plug portion by performing a selective etch of the undoped oxide to form a contact hole, removing a portion of the first insulating layer at a bottom of the contact hole, and forming a conductive contact in the contact hole.

Abstract: A method for forming a deep trench structure comprises the steps of providing a silicon substrate; forming a mask layer of a predetermined pattern on the silicon substrate to expose a portion of the silicon substrate; forming a first trench in the exposed portion of the silicon substrate, the first trench having a first depth; forming a nitride layer on the surfaces of the whole structure; forming a second trench in the first trench downward, the second trench having a second depth greater than the first depth; forming another nitride layer on the surfaces of the whole structure; and forming a third trench in the second trench downward, the third trench having a third depth greater than the second depth. The method of the present invention can make the whole trench have better etch uniformity, thereby obtaining good electrical performance.

Abstract: A method of forming a vertical memory device with a rectangular trench. First, a substrate covered by a photoresist layer is provided. Next, the photoresist layer is defined by a mask to form a rectangular opening, wherein the mask has two rectangular transparent patterns arranged with a predetermined interval. Next, the substrate is etched using the defined photoresist layer as a mask to form a single rectangular trench and the photoresist layer is then removed. Finally, a trench capacitor and a vertical transistor are successively formed in the rectangular trench to finish the vertical memory device.

Abstract: A method for forming a bottle trench. First, a substrate covered by a photoresist layer is rotated to a specific angle prior to performance of lithography, thereby forming a rectangular opening in the photoresist layer and exposing the substrate, in which edges of the rectangular opening are substantially parallel to the {110} plane of the substrate due to the rotation of the substrate. Next, the exposed substrate is etched to form a trench therein, in which the sidewall surface of the trench is the {110} plane of the substrate. Finally, isotropic etching is performed on the substrate of the lower portion of the trench using an etching shield layer formed on the sidewall of the upper portion of the trench as an etching mask, to form the bottle trench. The invention also discloses a method of fabricating a bottle trench capacitor.

Abstract: A novel metal gate structure includes a gate oxide layer formed on a surface of a silicon substrate, a doped silicon layer stacked on the gate oxide layer, a CVD ultra-thin titanium nitride film deposited on the doped silicon layer, a tungsten nitride layer stacked on the CVD ultra-thin titanium nitride film, a tungsten layer stacked on the tungsten nitride layer, and a nitride cap layer stacked on the tungsten layer. A liquid phase deposition (LPD) oxide spacer is formed on each sidewall of the metal gate stack. A silicon nitride spacer is formed on the LPD oxide spacer. The thickness of the CVD ultra-thin titanium nitride film is between 10 and 100 angstroms.

Abstract: The present invention relates to a method for growing a robust, high-quality gate oxide layer on a silicon surface. The resultant gate oxide layer made according to the present invention can pass the standard 50K times 14V high-voltage stress testing. The preferred embodiment of this invention includes a step of preliminary low-pressure N2O annealing that is carried out in an air-tight chamber at a temperature of less than 1000° C., a pressure below 0.2 torr, and N2O flow rate of below 8000 sccm. The preliminary low-pressure N2O annealing of the silicon surface is performed prior to the growth of high-quality gate oxide layer. In another preferred embodiment, N2O may be replaced with NO.

Abstract: A memory cell with a vertical transistor has a semiconductor silicon substrate with a deep trench, in which the deep trench has a first sidewall region and a second sidewall region. A first insulating layer is formed overlying the first sidewall region. A second insulating layer is formed overlying the second sidewall region, in which the thickness of the first insulating layer is larger than the thickness of the second insulating layer. A gate electrode layer is sandwiched between the first insulating layer and the second insulating layer. A buried strap out-diffusion region is formed in the substrate adjacent to the second sidewall region, in which the buried strap out-diffusion region is located near the lower portion of the second insulating layer.

Abstract: A method for manufacturing a single-ended buried strap used in semiconductor devices is disclosed. According to the present invention, a trench capacitor structure is formed in a semiconductor substrate, wherein the trench capacitor structure has a contact surface lower than a surface of the semiconductor substrate such that a recess is formed. Then, an insulative layer is formed on a sidewall of the recess. Next, impurities are implanted into a portion of the insulative layer, and the impurity-containing insulative layer is thereafter removed such that at least a portion of the contact surface and a portion of sidewall of the recess are exposed. A buried strap is sequentially formed on the exposed sidewall of the recess to be in contact with the exposed contact surface.

Abstract: A method of forming a single sided conductor and a semiconductor device having the same is provided. The method includes providing a substrate having an opening. The opening exposes a sidewall and an opening base surface. A tilted mask layer is formed in the opening. The tilted mask layer exposes the sidewall and a portion of the opening base surface. A dielectric layer is formed on the exposed sidewall and the exposed opening base surface. Then, the tilted mask layer is removed, and a conductive layer is formed over the substrate.

Abstract: Afin-type trench capacitor structure includes a buried plate diffused into a silicon substrate. The buried plate, which surrounds a bottle-shaped lower portion of the trench capacitor structure, is electrically connected to an upwardly extending annular poly electrode, thereby enabling the buried plate and the annular poly electrode to constitute a large-area capacitor electrode of the trench capacitor structure. A capacitor storage node consisting of a surrounding conductive layer, a central conductive layer and a collar conductive layer encompasses the upwardly extending annular poly electrode. A first capacitor dielectric layer isolates the capacitor storage node from the buried plate. A second capacitor dielectric layer and a third capacitor dielectric layer isolate the upwardly extending annular poly electrode from the capacitor storage node.

Abstract: A method of forming a conductive stud is provided. The method includes providing a substrate which has an upper surface and an opening. The opening exposes a portion of a vertical memory device. A conductive layer is formed over the substrate to fill the opening. A chemical mechanical polishing is performed on the conductive layer to form a conductive stud having an upper surface substantially lower than the upper surface of the substrate.