Abstract: A method for fabricating a vertical channel transistor device is provided. An opening is formed in a dielectric stack comprised of a pad nitride layer and a pad oxide layer. A plurality of epitaxial silicon growth and dry etching processes are carried out to form drain, vertical channel and source in the opening. Subsequently, sidewall gate dielectric and sidewall gate electrode are formed on the vertical channel. The present invention is suited for dynamic random access memory (DRAM) devices, particularly suited for very high-density trench-capacitor DRAM devices.

Abstract: A method for fabricating the semiconductor device comprises providing a semiconductor substrate having a device region and a testkey region. A first trench is formed in the device region and a second trench is formed in the testkey region. A conductive layer with a first etching selectivity is formed in the first and second trenches. A first implantation process is performed in a first direction to form a first doped region with a first impurity and an undoped region in the conductive layer simultaneously and respectively in the device region and in the testkey region. A second implantation process is performed in the second trench to form a second doped region with a second impurity in the conductive layer, wherein the conductive layer in the second trench has a second etching selectivity higher than the first etching selectivity.

Abstract: A method for fabricating recess channel MOS transistors of the present invention utilizes a lithography process to form trenches in the recess channel MOS transistors after finishing a STI process. Furthermore, the method of the present invention can make the critical dimension variation to be controlled in a range required in the precision semiconductor process. Therefore, the short problem between the transistors can be avoided.

Abstract: A manufacturing method of a volatile memory device is provided. The manufacturing method includes steps as follows. A sacrificial layer is formed in an area which is predetermined for forming a metal gate. Then, a thermal treatment process or other high temperature processes are performed in a peripheral circuit region. Next, a fabricating process of the metal gate is performed. Thus, the volatile memory device which has a lower contact resistance and a higher driving ability of the device can be produced, and thereby poor thermal stability and pollution of metal diffusion can be avoided.

Abstract: A method for fabricating line type recess channel MOS transistors utilizes a lithography process to form line type gate trenches in the line type recess channel MOS transistors before finishing a STI process. The method can further control the critical dimension variation in a range required in precision semiconductor processes. Therefore, the short problem between the transistors can be avoided.

Abstract: A method for fabricating a semiconductor memory device. A pair of neighboring trench capacitors is formed in a substrate. An insulating layer having a pair of connecting structures therein is formed on the substrate, in which the pair of connecting structures is electrically connected to the pair of neighboring trench capacitors. An active layer is formed on the insulating layer between the pair of connecting structures so as to cover the pair of connecting structures. A pair of gate structures is formed on the active layer to electrically connect to the pair of trench capacitors. A semiconductor memory device is also disclosed.

Abstract: A transistor structure includes a gate trench. The gate trench includes a bottle-shape bottom. The bottle-shape bottom includes a first conductive material wider than its top. The top includes a second material in a substrate, a gate structure on the gate trench and electrically connected to the first conductive material, a source/drain doping region adjacent to the gate trench and a gate channel between the source/drain doping region.

Abstract: A long channel semiconductor device and a manufacturing method thereof are provided. The method for forming a long channel semiconductor device includes: providing a substrate; forming a trench in the substrate with a trench bottom defining a first channel length; forming a spacer on a sidewall of the trench; recessing the trench bottom to form a recessed bottom defining a second channel length longer than the first channel length; forming a gate dielectric layer on the recessed bottom; forming a gate conductor on the gate dielectric layer; and forming source/drain regions in the substrate adjacent to the spacer.

Abstract: A deep trench device with a single sided connecting structure. The device comprises a substrate having a trench therein. A buried trench capacitor is disposed in a lower portion of the trench. An asymmetric collar insulator is disposed on an upper portion of the sidewall of the trench. A connecting structure is disposed in the upper portion of the trench, comprising an epitaxial silicon layer disposed on and adjacent to a relatively low portion of the asymmetric collar insulator and a connecting member disposed between the epitaxial silicon layer and a relatively high portion of the asymmetric collar insulator. A conductive layer is disposed between the relatively high and low portions of the asymmetric collar insulator, to electrically connect the buried trench capacitor and the connecting structure. A cap layer is disposed on the connecting structure. A fabrication method for a deep trench device is also disclosed.

Abstract: A method of fabricating self-aligned recess utilizing asymmetric poly spacer is disclosed. A semiconductor substrate having thereon a first pad layer and second pad layer is provided. A plurality of trenches is embedded in a memory array region of the semiconductor substrate. Each of the trenches includes a trench top layer that extrudes from a main surface of the semiconductor substrate. Asymmetric poly spacer is formed on one side of the extruding trench top layer and is used, after oxidized, as a mask for forming a recess in close proximity to the trenches.

Abstract: A semiconductor device includes a semiconductor substrate. The semiconductor substrate has a memory array region and a peripheral circuit region; a first active region and a second active region in the peripheral circuit region; a recessed gate disposed on the memory array region, comprising a first gate dielectric layer on the semiconductor substrate, wherein the first gate dielectric layer has a first thickness; and a second gate dielectric layer on the peripheral circuit region, wherein the second gate dielectric layer on the first active layer has a second thickness, and the second gate dielectric layer on the second active layer has a third thickness.

Abstract: A method for fabricating a MOS transistor with a recess channel, including: providing a substrate with a plurality of trench capacitors therein, wherein a trench top oxide is positioned on top of each trench capacitor and extended away from the substrate surface; forming a first spacer on side walls of the trench top oxide; forming a second spacer on the first spacer; defining a plurality of active areas, wherein each of the active areas is parallel with each other and comprises at least two of the trench capacitors; forming an isolation area between each of the active area; etching the substrate of the active area by using the second spacer as a mask to form a trench in the active area; removing the second spacer to expose a portion of the substrate, and etching the exposed substrate to enlarge the trench; and forming a gate structure in the trench.

Abstract: A method for fabricating a vertical channel transistor device is provided. An opening is formed in a dielectric stack comprised of a pad nitride layer and a pad oxide layer. A plurality of epitaxial silicon growth and dry etching processes are carried out to form drain, vertical channel and source in the opening. Subsequently, sidewall gate dielectric and sidewall gate electrode are formed on the vertical channel. The present invention is suited for dynamic random access memory (DRAM) devices, particularly suited for very high-density trench-capacitor DRAM devices.

Abstract: A method of fabricating a deep trench is provided, by which a trench is formed in the substrate initially. Then, a block layer is formed on the substrate surface of the upper portion of the trench. After that, a pad oxide layer is formed on the substrate surface of the lower portion of the trench. Next, a plurality of hemispherical silicon grains is formed on the substrate and exposes a portion of the pad oxide layer. Then, by using the hemispherical silicon grains as a mask, a portion of the pad oxide layer is removed so as to form a patterned pad oxide layer. Continually, the hemispherical silicon grains and the substrate exposed by the patterned pad oxide layer are removed. Finally, the patterned pad oxide layer is removed.

Abstract: A memory device is disclosed. A substrate is provided. A plurality of pillars is disposed on the substrate. Each pillar has a plurality of epitaxial layers, has a first sidewall and a second sidewall. A trench is formed between the pillars. A common bottom electrode is disposed in a lower portion of the trench and surrounded by a node dielectric layer. A first insulating layer is disposed on the common bottom electrode inside the trench. A plurality of gate structures is disposed on the first sidewall and inside the trench. A second insulating layer is disposed inside the trench and adjacent to the gate structures. A third insulating layer, body line, and fourth insulating layer are respectively disposed on the substrate and located between the second insulating layer and the second sidewall.

Abstract: A method of fabricating self-aligned recess utilizing asymmetric poly spacer is disclosed. A semiconductor substrate having thereon a first pad layer and second pad layer is provided. A plurality of trenches is embedded in a memory array region of the semiconductor substrate. Each of the trenches includes a trench top layer that extrudes from a main surface of the semiconductor substrate. Asymmetric poly spacer is formed on one side of the extruding trench top layer and is used, after oxidized, as a mask for forming a recess in close proximity to the trenches.

Abstract: The present invention provides a semiconductor structure and the forming method thereof. The structure includes a substrate having a plurality of stacks; a conformal layer on the substrate and a portion of sidewalls of the plurality of the stacks; and a plurality of plugs between the plurality of stacks. In addition, the present invention also provides a method of forming the semiconductor structure, comprising steps of providing a substrate; forming a plurality of stacks on the substrate; forming a conformal layer on the stacks and on the substrate; removing a portion of the conformal layer to expose a sidewall and a top surface of the plurality of stacks; and forming a plurality of plugs between the stacks.

Abstract: A method of forming a conductive stud is provided. The method includes providing a substrate which has an upper surface and an opening. The opening exposes a portion of a vertical memory device. A conductive layer is formed over the substrate to fill the opening. A chemical mechanical polishing is performed on the conductive layer to form a conductive stud having an upper surface substantially lower than the upper surface of the substrate.

Abstract: A method for fabricating a vertical channel transistor device is provided. An opening is formed in a dielectric stack comprised of a pad nitride layer and a pad oxide layer. A plurality of epitaxial silicon growth and dry etching processes are carried out to form drain, vertical channel and source in the opening. Subsequently, sidewall gate dielectric and sidewall gate electrode are formed on the vertical channel. The present invention is suited for dynamic random access memory (DRAM) devices, particularly suited for very high-density trench-capacitor DRAM devices.

Abstract: A method of fabricating self-aligned gate trench utilizing trench top oxide (TTO) poly spacer is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad nitride layer is provided. A plurality of trench capacitors are embedded in a memory array region of the semiconductor substrate. Each of the trench capacitors has a TTO that extrudes from a main surface of the semiconductor substrate. Poly spacers are formed on two opposite sides of the extruding TTO and are used, after oxidized, as an etching hard mask for etching a recessed gate trench in close proximity to the trench capacitor.