Patents by Inventor Shibly S. Ahmed
Shibly S. Ahmed has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11368155Abstract: Embodiments of the disclosure provide an input output (IO) structure in which complimentary nodes of a level shifter are utilized to logically block the output of the IO structure from switching until both power supplies to the IO structure are powered up. An illustrative level shifter includes: a cross-coupled pair of PFETs configured to output complimentary voltage values at a first node and a second node; a control circuit configured to select which of the complementary voltage values are output to the first node and second node; a logic inverter having an input coupled to the first node and an output coupled to a third node; and a NAND gate having inputs coupled to the second node and third node and that generates a level shifted output.Type: GrantFiled: December 4, 2020Date of Patent: June 21, 2022Assignee: GlobalFoundries U.S. Inc.Inventors: Dzung T. Tran, Shibly S. Ahmed
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Publication number: 20220182058Abstract: Embodiments of the disclosure provide an input output (IO) structure in which complimentary nodes of a level shifter are utilized to logically block the output of the IO structure from switching until both power supplies to the IO structure are powered up. An illustrative level shifter includes: a cross-coupled pair of PFETs configured to output complimentary voltage values at a first node and a second node; a control circuit configured to select which of the complementary voltage values are output to the first node and second node; a logic inverter having an input coupled to the first node and an output coupled to a third node; and a NAND gate having inputs coupled to the second node and third node and that generates a level shifted output.Type: ApplicationFiled: December 4, 2020Publication date: June 9, 2022Inventors: Dzung T. Tran, Shibly S. Ahmed
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Patent number: 9759764Abstract: A method includes varying spacing between at least one of a source region or a drain region and a well contact region to create a group of configurations. The method further includes determining an effect of latchup on each configuration.Type: GrantFiled: December 15, 2014Date of Patent: September 12, 2017Assignee: Cypress Semiconductor CorporationInventors: Chuan Lin, Dong-Hyuk Ju, Imran Khan, Jun Kang, Shibly S. Ahmed
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Patent number: 8912014Abstract: A method includes varying spacing between at least one of a source region or a drain region and a well contact region to create a group of configurations. The method further includes determining an effect of latchup on each configuration.Type: GrantFiled: January 18, 2006Date of Patent: December 16, 2014Assignee: Spansion LLCInventors: Chuan Lin, Dong-Hyuk Ju, Imran Khan, Jun Kang, Shibly S. Ahmed
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Patent number: 8536011Abstract: A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.Type: GrantFiled: March 29, 2011Date of Patent: September 17, 2013Assignee: Spansion LLCInventors: Shibly S. Ahmed, Jun Kang, Hsiao-Han Thio, Imran Khan, Dong-Hyuk Ju, Chuan Lin
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Patent number: 8217450Abstract: A double-gate semiconductor device includes a substrate, an insulating layer, a fin and two gates. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. A first gate is formed on the insulating layer and is adjacent a first sidewall of the fin. The second gate is formed on the insulating layer and is adjacent a second sidewall of the fin opposite the first sidewall. The first and second gates both include a conductive material and are electrically separated by the fin.Type: GrantFiled: February 3, 2004Date of Patent: July 10, 2012Assignee: Globalfoundries, Inc.Inventors: Bin Yu, Shibly S. Ahmed, Haihong Wang
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Publication number: 20110176363Abstract: A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.Type: ApplicationFiled: March 29, 2011Publication date: July 21, 2011Applicant: SPANSION LLCInventors: Shibly S. AHMED, Jun KANG, Hsiao-Han THIO, Imran KHAN, Dong-Hyuk JU, Chuan LIN
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Patent number: 7939440Abstract: A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.Type: GrantFiled: June 15, 2005Date of Patent: May 10, 2011Assignee: Spansion LLCInventors: Shibly S. Ahmed, Jun Kang, Hsiao-Han Thio, Imran Khan, Dong-Hyuk Ju, Chuan Lin
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Patent number: 7541267Abstract: A method includes forming a first rectangular mesa from a layer of semiconducting material and forming a first dielectric layer around the first mesa. The method further includes forming a first rectangular mask over a first portion of the first mesa leaving an exposed second portion of the first mesa and etching the exposed second portion of the first mesa to produce a reversed T-shaped fin from the first mesa.Type: GrantFiled: June 20, 2007Date of Patent: June 2, 2009Assignee: Advanced Micro Devices, Inc.Inventors: Haihong Wang, Shibly S. Ahmed, Ming-Ren Lin, Bin Yu
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Patent number: 7498225Abstract: A method for forming fin structures for a semiconductor device that includes a substrate and a dielectric layer formed on the substrate is provided. The method includes etching the dielectric layer to form a first structure, depositing an amorphous silicon layer over the first structure, and etching the amorphous silicon layer to form second and third fin structures adjacent first and second side surfaces of the first structure. The second and third fin structures may include amorphous silicon material. The method further includes depositing a metal layer on upper surfaces of the second and third fin structures, performing a metal-induced crystallization operation to convert the amorphous silicon material of the second and third fin structures to a crystalline silicon material, and removing the first structure.Type: GrantFiled: July 5, 2006Date of Patent: March 3, 2009Assignee: Advanced Micro Devices, Inc.Inventors: Haihong Wang, Shibly S. Ahmed, Ming-Ren Lin, Bin Yu
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Patent number: 7432558Abstract: A semiconductor device may include a substrate and an insulating layer formed on the substrate. A fin may be formed on the insulating layer. The fin may include a side surface and a top surface, and the side surface may have a <100> orientation. A first gate may be formed on the insulating layer proximate to the side surface of the fin.Type: GrantFiled: June 9, 2004Date of Patent: October 7, 2008Assignee: Advanced Micro Devices, Inc.Inventors: Shibly S. Ahmed, Judy Xilin An, Srikanteswara Dakshina-Murthy, Cyrus E. Tabery, Bin Yu
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Patent number: 7262104Abstract: Multiple semiconductor devices are formed with different threshold voltages. According to one exemplary implementation, first and second semiconductor devices are formed and doped differently, resulting in different threshold voltages for the first and second semiconductor devices.Type: GrantFiled: June 2, 2004Date of Patent: August 28, 2007Assignee: Advanced Micro Devices, Inc.Inventors: Haihong Wang, Shibly S. Ahmed, Bin Yu
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Patent number: 7256455Abstract: A semiconductor device may include a substrate, an insulating layer formed on the substrate and a conductive fin formed on the insulating layer. The conductive fin may include a number of side surfaces and a top surface. The semiconductor device may also include a source region formed on the insulating layer adjacent a first end of the conductive fin and a drain region formed on the insulating layer adjacent a second end of the conductive fin. The semiconductor device may further include a metal gate formed on the insulating layer adjacent the conductive fin in a channel region of the semiconductor device.Type: GrantFiled: November 25, 2003Date of Patent: August 14, 2007Assignee: Advanced Micro Devices, Inc.Inventors: Shibly S. Ahmed, Haihong Wang, Bin Yu
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Patent number: 7250645Abstract: A fin field effect transistor (FinFET) includes a reversed T-shaped fin. The FinFET further includes source and drain regions formed adjacent the reversed T-shaped fin. The FinFET further includes a dielectric layer formed adjacent surfaces of the fin and a gate formed adjacent the dielectric layer.Type: GrantFiled: January 22, 2004Date of Patent: July 31, 2007Assignee: Advanced Micro Devices, Inc.Inventors: Haihong Wang, Shibly S. Ahmed, Ming-Ren Lin, Bin Yu
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Patent number: 7186599Abstract: A method of forming a fin field effect transistor includes forming a fin and forming a source region on a first end of the fin and a drain region on a second end of the fin. The method further includes forming a dummy gate with a first semi-conducting material in a first pattern over the fin and forming a dielectric layer around the dummy gate. The method also includes removing the first semi-conducting material to leave a trench in the dielectric layer corresponding to the first pattern, thinning a portion of the fin exposed within the trench, and forming a metal gate within the trench.Type: GrantFiled: January 12, 2004Date of Patent: March 6, 2007Assignee: Advanced Micro Devices, Inc.Inventors: Shibly S. Ahmed, Haihong Wang, Bin Yu
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Patent number: 7179692Abstract: A method of forming a semiconductor device includes forming a fin on an insulating layer, where the fin includes a number of side surfaces, a top surface and a bottom surface. The method also includes forming a gate on the insulating layer, where the gate has a substantially U-shaped cross-section at a channel region of the semiconductor device.Type: GrantFiled: August 9, 2004Date of Patent: February 20, 2007Assignee: Advanced Micro Devices, Inc.Inventors: Bin Yu, Shibly S. Ahmed, Judy Xilin An, Srikanteswara Dakshina-Murthy, Zoran Krivokapic, Haihong Wang
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Patent number: 7125776Abstract: A method of manufacturing a MOSFET type semiconductor device includes planarizing a gate material layer that is deposited over a channel. The planarization is performed in a multi-step process that includes an initial “rough” planarization and then a “fine” planarization. The slurry used for the finer planarization may include added material that tends to adhere to low areas of the gate material.Type: GrantFiled: January 7, 2005Date of Patent: October 24, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Krishnashree Achuthan, Shibly S. Ahmed, Haihong Wang, Bin Yu
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Patent number: 7095065Abstract: A semiconductor device may include a substrate and an insulating layer formed on the substrate. A first device may be formed on the insulating layer, including a first fin. The first fin may be formed on the insulating layer and may have a first fin aspect ratio. A second device may be formed on the insulating layer, including a second fin. The second fin may be formed on the insulating layer and may have a second fin aspect ratio different from the first fin aspect ratio.Type: GrantFiled: August 5, 2003Date of Patent: August 22, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Bin Yu, Shibly S. Ahmed, Haihong Wang
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Patent number: 7091068Abstract: A method of manufacturing a semiconductor device may include forming a fin structure on an insulator and depositing a gate material over the fin structure. The method may also include forming a sacrificial material over the gate material and planarizing the sacrificial material. An antireflective coating may be deposited on the planarized sacrificial material. A gate structure may then be formed by etching the gate material.Type: GrantFiled: December 6, 2002Date of Patent: August 15, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Shibly S. Ahmed, Cyrus E. Tabery, Bin Yu
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Patent number: 7084018Abstract: A method of reducing buried oxide undercut during FinFET formation includes forming a fin on a buried oxide layer and forming a source region adjacent a first end of the fin and a drain region adjacent a second end of the fin. The method further includes forming a sacrificial oxide layer over the fin and source and drain regions and forming a gate over the fin, wherein the sacrificial oxide layer reduces undercutting of the buried oxide layer during gate formation.Type: GrantFiled: May 5, 2004Date of Patent: August 1, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Shibly S. Ahmed, Bin Yu