Patents by Inventor Shibly S. Ahmed

Shibly S. Ahmed has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dual silicon layer for chemical mechanical polishing planarization
    Patent number: 6812076
    Abstract: A FinFet-type semiconductor device includes a fin structure on which a relatively thin amorphous silicon layer and then an undoped polysilicon layer is formed. The semiconductor device may be planarized using a chemical mechanical polishing (CMP) in which the amorphous silicon layer acts as a stop layer to prevent damage to the fin structure.
    Type: Grant
    Filed: January 8, 2004
    Date of Patent: November 2, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Krishnashree Achuthan, Shibly S. Ahmed, Haihong Wang, Bin Yu
  • Method for forming a fin in a finFET device
    Patent number: 6787854
    Abstract: A method for forming a fin structure on a silicon-on-insulator (SOI) wafer that includes a silicon layer on an insulating layer that is formed over a semiconductor substrate includes etching the silicon layer using a first etch procedure, etching, following the first etch procedure, the silicon layer using a second etch procedure, and etching, following the second etch procedure, the silicon layer using a third etch procedure to form a T-shaped fin structure.
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: September 7, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Chih-Yuh Yang, Shibly S. Ahmed, Srikanteswara Dakshina-Murthy, Cyrus E. Tabery, Haihong Wang, Bin Yu
  • Systems and methods for forming dense n-channel and p-channel fins using shadow implanting
    Patent number: 6787406
    Abstract: A method facilitates the doping of fins of a semiconductor device that includes a substrate. The method includes forming fin structures on the substrate, where each of the fin structures includes a cap formed on a fin. The method further includes performing a first tilt angle implant process to dope a first one of the fins with n-type impurities and performing a second tilt angle implant process to dope a second one of the fins with p-type impurities.
    Type: Grant
    Filed: August 12, 2003
    Date of Patent: September 7, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Wiley Eugene Hill, Shibly S. Ahmed, Haihong Wang, Bin Yu
  • Method using planarizing gate material to improve gate critical dimension in semiconductor devices
    Patent number: 6787439
    Abstract: A method of manufacturing a semiconductor device may include forming a fin structure on an insulator. The fin structure may include side surfaces and a top surface. The method may also include depositing a gate material over the fin structure and planarizing the deposited gate material. An antireflective coating may be deposited on the planarized gate material, and a gate structure may be formed out of the planarized gate material using the antireflective coating.
    Type: Grant
    Filed: November 8, 2002
    Date of Patent: September 7, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Shibly S. Ahmed, Cyrus E. Tabery, Haihong Wang, Bin Yu
  • Double gate semiconductor device having separate gates
    Publication number: 20040126975
    Abstract: A semiconductor device may include a substrate and an insulating layer formed on the substrate. A fin may be formed on the insulating layer and may include a number of side surfaces and a top surface. A first gate may be formed on the insulating layer proximate to one of the number of side surfaces of the fin. A second gate and may be formed on the insulating layer separate from the first gate and proximate to another one of number of side surfaces of the fin.
    Type: Application
    Filed: June 24, 2003
    Publication date: July 1, 2004
    Inventors: Shibly S. Ahmed, Haihong Wang, Bin Yu
  • Dual silicon layer for chemical mechanical polishing planarization
    Patent number: 6756643
    Abstract: A FinFET-type semiconductor device includes a fin structure on which a relatively thin amorphous silicon layer and then an undoped polysilicon layer is formed. The semiconductor device may be planarized using a chemical mechanical polishing (CMP) in which the amorphous silicon layer acts as a stop layer to prevent damage to the fin structure.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: June 29, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Krishnashree Achuthan, Shibly S. Ahmed, Haihong Wang, Bin Yu
  • Double gate semiconductor device having a metal gate
    Publication number: 20040110097
    Abstract: A method of manufacturing a semiconductor device may include forming a fin structure on an insulator and forming a gate structure over a channel portion of the fin structure. The method may also include forming a sacrificial oxide layer around the gate structure and removing the gate structure to define a gate recess within the sacrificial oxide layer. A metal gate may be formed in the gate recess, and the sacrificial oxide layer may be removed.
    Type: Application
    Filed: November 25, 2003
    Publication date: June 10, 2004
    Inventors: Shibly S. Ahmed, Haihong Wang, Bin Yu
  • Planarizing gate material to improve gate critical dimension in semiconductor devices
    Publication number: 20040092062
    Abstract: A method of manufacturing a semiconductor device may include forming a fin structure on an insulator. The fin structure may include side surfaces and a top surface. The method may also include depositing a gate material over the fin structure and planarizing the deposited gate material. An antireflective coating may be deposited on the planarized gate material, and a gate structure may be formed out of the planarized gate material using the antireflective coating.
    Type: Application
    Filed: November 8, 2002
    Publication date: May 13, 2004
    Inventors: Shibly S. Ahmed, Cyrus E. Tabery, Haihong Wang, Bin Yu
  • Semiconductor device having a U-shaped gate structure
    Publication number: 20040075121
    Abstract: A double-gate semiconductor device includes a substrate, an insulating layer, a fin and a gate. The insulating layer is formed on the substrate and the gate is formed on the insulating layer. The fin has a number of side surfaces, a top surface and a bottom surface. The bottom surface and at least a portion of the side surfaces of the fin are surrounded by the gate. The gate material surrounding the fin has a U-shaped cross-section at a channel region of the semiconductor device.
    Type: Application
    Filed: October 22, 2002
    Publication date: April 22, 2004
    Inventors: Bin Yu, Shibly S. Ahmed, Judy Xilin An, Srikanteswara Dakshina-Murthy, Zoran Krivokapic, Haihong Wang
  • Damascene gate process with sacrificial oxide in semiconductor devices
    Patent number: 6686231
    Abstract: A method of manufacturing a semiconductor device may include forming a fin structure on an insulator and forming a gate structure over a channel portion of the fin structure. The method may also include forming a sacrificial oxide layer around the gate structure and removing the gate structure to define a gate recess within the sacrificial oxide layer. A metal gate may be formed in the gate recess, and the sacrificial oxide layer may be removed.
    Type: Grant
    Filed: December 6, 2002
    Date of Patent: February 3, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Shibly S. Ahmed, Haihong Wang, Bin Yu
  • Double gate semiconductor device having separate gates
    Patent number: 6611029
    Abstract: A semiconductor device may include a substrate and an insulating layer formed on the subtrate. A fin may be formed on the insulating layer and may include a number of side surfaces and a top surface. A first gate may be formed on the insulating layer proximate to one of the number of side surfaces of the fin. A second gate and may be formed on the insulating layer separate from the first gate and proximate to another one of number of side surfaces of the fin.
    Type: Grant
    Filed: November 8, 2002
    Date of Patent: August 26, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Shibly S. Ahmed, Haihong Wang, Bin Yu