Patents by Inventor Shidhartha Das
Shidhartha Das has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11550965Abstract: Analytics processing circuitry can include a data scavenger and a data analyzer coupled to receive the data from the data scavenger. The data scavenger collects data from at least one element of interest of a plurality of elements of interest of an IC. The data analyzer identifies patterns in the data from the data scavenger over a time frame or for a snapshot of time based on a predefined metric. The analytics processing circuitry can further include a moderator and a risk predictor. The risk predictor generates a risk assessment regarding whether the data collected by the data scavenger is indicative of normal behavior or abnormal behavior based at least on the output of the data analyzer and a behavioral model for the IC, which can be device and application specific. A threat response can be performed based on the risk assessment.Type: GrantFiled: April 22, 2020Date of Patent: January 10, 2023Assignee: ARM LIMITEDInventors: Subbayya Chowdary Yanamadala, Jeremy Patrick Dubeuf, Carl Wayne Vineyard, Matthias Lothar Boettcher, Hugo John Martin Vincent, Shidhartha Das
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Publication number: 20220399895Abstract: Various implementations described herein are directed to a device with a voltage-controlled oscillator that receives an enable signal, receives a reset signal, and provides internal pulse signals including one or more coarse internal pulse signals and multiple fine internal pulse signals. The device may have a coarse sampler that receives the one or more coarse internal pulse signal and provides a coarse sampled output signal. The device may have a fine sampler that receives the multiple fine internal pulse signals and provides a fine sampled output signal.Type: ApplicationFiled: June 10, 2021Publication date: December 15, 2022Inventors: Shidhartha Das, Yunpeng Cai, Supreet Jeloka
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Patent number: 11501150Abstract: Various implementations are related to an apparatus with memory cells arranged in columns and rows, and the memory cells are accessible with a column control voltage for accessing the memory cells via the columns and a row control voltage for accessing the memory cells via the rows. The apparatus may include neural network circuitry having neuronal junctions that are configured to receive, record, and provide information related to incoming voltage spikes associated with input signals based on resistance through the neuronal junctions. The apparatus may include stochastic re-programmer circuitry that receives the incoming voltage spikes, receives the information provided by the neuronal junctions, and reconfigure the information recorded in the neuronal junctions based on the incoming voltage spikes associated with the input signals along with a programming control signal provided by the memory circuitry.Type: GrantFiled: May 20, 2020Date of Patent: November 15, 2022Assignee: Arm LimitedInventors: Mbou Eyole, Shidhartha Das, Fernando Garcia Redondo
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Patent number: 11494256Abstract: An apparatus comprises a plurality of redundant processing units to perform data processing redundantly in lockstep; common mode fault detection circuitry to detect an event indicative of a potential common mode fault affecting each of the plurality of redundant processing units; a memory shared between the plurality of redundant processing units; and memory checking circuitry to perform a memory scanning operation to scan at least part of the memory for errors; in which the memory checking circuitry performs the memory scanning operation in response to a common mode fault signal generated by the common mode fault detection circuitry indicating that the event indicative of a potential common mode fault has been detected.Type: GrantFiled: June 6, 2019Date of Patent: November 8, 2022Assignee: Arm LimitedInventors: Milosch Meriac, Emre Özer, Xabier Iturbe, Balaji Venu, Shidhartha Das
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Patent number: 11468305Abstract: The present disclosure advantageously provides a hybrid memory artificial neural network hardware accelerator that includes a communication bus interface, a static memory, a non-refreshed dynamic memory, a controller and a computing engine. The static memory stores at least a portion of an ANN model. The ANN model includes an input layer, one or more hidden layers and an output layer, ANN basis weights, input data and output data. The non-refreshed dynamic memory is configured to store ANN custom weights for the input, hidden and output layers, and output data. For each layer or layer portion, the computing engine generates the ANN custom weights based on the ANN basis weights, stores the ANN custom weights in the non-refreshed dynamic memory, executes the layer or layer portion, based on inputs and the ANN custom weights, to generate layer output data, and stores the layer output data.Type: GrantFiled: March 18, 2020Date of Patent: October 11, 2022Assignee: Arm LimitedInventors: Urmish Ajit Thakker, Shidhartha Das, Ganesh Suryanarayan Dasika
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Patent number: 11444625Abstract: Various implementations described herein are related to a device. The device may include first circuitry that receives a clock signal and provides one or more phase-shifted pulse signals based on the clock signal. The device may include second circuitry that receives an input voltage, receives the clock signal, and provides an internal control signal based on the input voltage and the clock signal. The device may include third circuitry that receives the internal control signal, receives the one or more phase-shifted pulse signals, and provides an output clock signal based on the internal control signal and the one or more phase-shifted pulse signals.Type: GrantFiled: November 24, 2020Date of Patent: September 13, 2022Assignee: Arm LimitedInventors: Benoit Labbe, Shidhartha Das, Thanusree Achuthan
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Patent number: 11423985Abstract: In a particular implementation, a method includes: providing a first voltage to a word-line coupled to a first transistor device; providing a second voltage to a bit-line coupled to the first transistor device; providing a third voltage to a source-line coupled between a programmable resistive device and a voltage control element. Also, the first transistor device is coupled to the programmable resistive device and the voltage control element, where the programmable resistive device is configured to replace a first data value by writing a second data value in the programmable resistive device. Moreover, in response to a voltage difference across the programmable resistive device exceeding a particular threshold, limiting the voltage difference by one of reducing the second voltage on the bit-line or increasing the third voltage on the source-line.Type: GrantFiled: September 25, 2019Date of Patent: August 23, 2022Assignee: Arm LimitedInventors: Fernando Garcia Redondo, Shidhartha Das, Glen Arnold Rosendale, George McNeil Lattimore, Mudit Bhargava
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Publication number: 20220199125Abstract: Various implementations described herein are related to a device having voltage regulation architecture with multiple layers arranged in a multi-layer structure. The device may include one or more layers of the multiple layers with voltage regulation circuitry that may be configured to manage at least one of process variation and temperature variation between the multiple layers of the multi-layer structure.Type: ApplicationFiled: June 10, 2021Publication date: June 23, 2022Inventors: Supreet Jeloka, Saurabh Pijuskumar Sinha, Shidhartha Das, Mudit Bhargava, Rahul Mathur
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Patent number: 11366779Abstract: A chip-carrier package includes a data processing system having one or more slave dies, a master die and a system bus. Each slave die includes a slave device and a slave-side wireless bus interface (WBI) coupled to the slave device. The master die includes a master device, one or more bus-side WBIs coupled to the master device. Each bus-side WBI is configured to be wirelessly coupled to at least one slave-side WBI of the one or more slave dies and a system bus. The system bus includes the one or more bus-side WBIs and the slave-side WBIs of the one or more slave-side dies. The system bus is configured to exchange information between the master device and the slave devices of the one or more slave dies.Type: GrantFiled: November 15, 2019Date of Patent: June 21, 2022Assignees: Arm Limited, ECS Partners LimitedInventors: Benjamin James Fletcher, James Edward Myers, Shidhartha Das, Terrence Sui Tung Mak
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Publication number: 20220179658Abstract: A method and apparatus for performing refactored multiply-and-accumulate operations is provided. A summing array includes a plurality of non-volatile memory elements arranged in columns. Each non-volatile memory element in the summing array is programmed to a high resistance state or a low resistance state based on weights of a neural network. The summing array is configured to generate a summed signal for each column based, at least in part, on a plurality of input signals. A multiplying array is coupled to the summing array, and includes a plurality of non-volatile memory elements. Each non-volatile memory element in the multiplying array is programmed to a different conductance level based on the weights of the neural network. The multiplying array is configured to generate an output signal based, at least in part, on the summed signals from the summing array.Type: ApplicationFiled: February 17, 2022Publication date: June 9, 2022Applicant: Arm LimitedInventors: Matthew Mattina, Shidhartha Das, Glen Arnold Rosendale, Fernando Garcia Redondo
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Patent number: 11355192Abstract: According to one embodiment of the present disclosure, a device comprises a latching circuitry, where the latching circuitry comprises at least one correlated electron random access memory (CeRAM) element. The latching circuitry further comprises a control circuit coupled to the at least one CeRAM element. The control circuit is configured to receive at least one control signal. Based on the at least one control signal, perform at least one of storing data into the latching circuitry and outputting data from the latching circuitry.Type: GrantFiled: September 20, 2017Date of Patent: June 7, 2022Assignee: ARM Ltd.Inventors: Robert Campbell Aitken, Vikas Chandra, Bal S. Sandhu, George McNeil Lattimore, Shidhartha Das, John Philip Biggs, Parameshwarappa Anand Kumar Savanth, James Edward Myers
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Publication number: 20220163576Abstract: An integrated circuit includes a first circuit and a power meter coupled to the first circuit at selected proxy locations. The power meter includes circuitry for generating toggle data, such as signal transitions or signal levels, from signals at the proxy locations and combiner circuitry for combining the toggle data in a first time window with a set of weight value to produce a measure of power usage in the first circuit. The proxy locations and weight values are selected automatically based on simulated or emulated signals from a larger set of locations in the first circuit and associated power usage in the first circuit.Type: ApplicationFiled: March 31, 2021Publication date: May 26, 2022Applicant: Arm LimitedInventors: Xiaoqing Xu, Zhiyao Xie, Shidhartha Das
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Publication number: 20220164511Abstract: A power meter for measuring power usage in a circuit includes preprocessor and a weighting network. The pre-processor is configured to receive toggle data for a number of power proxy signals in the circuit for a plurality of clock cycles of the circuit in a first time window. The power proxy signals and weighting values are determined automatically from simulated or emulated toggle data. For each power proxy signal, the pre-processor averages the toggle data over one or more clock cycles in one or more second time windows, within the first time window, to provide averaged toggle data, and outputs the averaged toggle data for each second time window. The weighting network is configured to combine the averaged toggle data from the power proxy signals, based on a set of weight values, to provide a measure of the power usage.Type: ApplicationFiled: March 31, 2021Publication date: May 26, 2022Applicant: Arm LimitedInventors: Xiaoqing Xu, Zhiyao Xie, Shidhartha Das, Matthew James Walker, Kumara Guru Palaniswamy, Matthew Paul Elwood
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Publication number: 20220166436Abstract: Various implementations described herein are related to a device. The device may include first circuitry that receives a clock signal and provides one or more phase-shifted pulse signals based on the clock signal. The device may include second circuitry that receives an input voltage, receives the clock signal, and provides an internal control signal based on the input voltage and the clock signal. The device may include third circuitry that receives the internal control signal, receives the one or more phase-shifted pulse signals, and provides an output clock signal based on the internal control signal and the one or more phase-shifted pulse signals.Type: ApplicationFiled: November 24, 2020Publication date: May 26, 2022Inventors: Benoit Labbe, Shidhartha Das, Thanusree Achuthan
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Patent number: 11334788Abstract: Broadly speaking, embodiments of the present techniques provide a reconfigurable hardware-based artificial neural network, wherein weights for each neural network node of the artificial neural network are obtained via training performed external to the neural network.Type: GrantFiled: June 14, 2017Date of Patent: May 17, 2022Assignee: Arm LimitedInventors: Shidhartha Das, Rune Holm
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Publication number: 20220101085Abstract: A non-volatile memory (NVM) crossbar for an artificial neural network (ANN) accelerator is provided. The NVM crossbar includes row signal lines configured to receive input analog voltage signals, multiply-and-accumulate (MAC) column signal lines, a correction column signal line, a MAC cell disposed at each row signal line and MAC column signal line intersection, and a correction cell disposed at each row signal line and correction column signal line intersection. Each MAC cell includes one or more programmable NVM elements programmed to an ANN unipolar weight, and each correction cell includes one or more programmable NVM elements. Each MAC column signal line generates a MAC signal based on the input analog voltage signals and the respective MAC cells, and the correction column signal line generates a correction signal based on the input analog voltage signals and the correction cells. Each MAC signal is corrected based on the correction signal.Type: ApplicationFiled: September 29, 2020Publication date: March 31, 2022Applicant: Arm LimitedInventors: Fernando Garcia Redondo, Shidhartha Das, Paul Nicholas Whatmough, Glen Arnold Rosendale
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Patent number: 11232236Abstract: A method and authenticator for authenticating a device in a system using the electrical properties of the device is disclosed. Embodiments of the disclosure enable authentication by receiving a plurality of input seed values from a requestor. For each input seed value, load stimuli are generated to produce an electrical load sequence on a power delivery network powering at least part of the system. Noise induced in the power delivery network is measured in response to the electrical load sequence using one or more sensors located on the power delivery network. Based on the measured noise, a dynamic response property (magnitude and phase response as a function of frequency) of the power delivery network corresponding to a respective input seed value can be determined and returned to the requestor.Type: GrantFiled: April 18, 2019Date of Patent: January 25, 2022Assignee: Arm LimitedInventors: Hugo John Martin Vincent, Shidhartha Das, Milosch Meriac, Vasileios Tenentes
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Publication number: 20210365764Abstract: Various implementations are related to an apparatus with memory cells arranged in columns and rows, and the memory cells are accessible with a column control voltage for accessing the memory cells via the columns and a row control voltage for accessing the memory cells via the rows. The apparatus may include neural network circuitry having neuronal junctions that are configured to receive, record, and provide information related to incoming voltage spikes associated with input signals based on resistance through the neuronal junctions. The apparatus may include stochastic re-programmer circuitry that receives the incoming voltage spikes, receives the information provided by the neuronal junctions, and reconfigure the information recorded in the neuronal junctions based on the incoming voltage spikes associated with the input signals along with a programming control signal provided by the memory circuitry.Type: ApplicationFiled: May 20, 2020Publication date: November 25, 2021Inventors: Mbou Eyole, Shidhartha Das, Femando Garcia Redondo
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Publication number: 20210334373Abstract: A moderator system that can receive outputs of various stages of the security analytic framework and can receive input from external sources to provide information about emerging styles of attacks. One or more models/behavioral profiles can be curated by the moderator system, and the moderator system can provide updates to components of the security analytics framework.Type: ApplicationFiled: April 22, 2020Publication date: October 28, 2021Inventors: Subbayya Chowdary YANAMADALA, Jeremy Patrick DUBEUF, Carl Wayne VINEYARD, Matthias Lothar BOETTCHER, Hugo John Martin VINCENT, Shidhartha DAS
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Publication number: 20210334415Abstract: Analytics processing circuitry can include a data scavenger and a data analyzer coupled to receive the data from the data scavenger. The data scavenger collects data from at least one element of interest of a plurality of elements of interest of an IC. The data analyzer identifies patterns in the data from the data scavenger over a time frame or for a snapshot of time based on a predefined metric. The analytics processing circuitry can further include a moderator and a risk predictor. The risk predictor generates a risk assessment regarding whether the data collected by the data scavenger is indicative of normal behavior or abnormal behavior based at least on the output of the data analyzer and a behavioral model for the IC, which can be device and application specific. A threat response can be performed based on the risk assessment.Type: ApplicationFiled: April 22, 2020Publication date: October 28, 2021Inventors: Subbayya Chowdary YANAMADALA, Jeremy Patrick DUBEUF, Carl Wayne VINEYARD, Matthias Lothar BOETTCHER, Hugo John Martin VINCENT, Shidhartha DAS