Abstract: There is provided a system comprising: a storage device having a storage portion comprising a plurality of bitcells coupled to respective first signal lines and second signal lines and control logic to alter a memory state of the plurality of bitcells via the first signal lines and second signal lines; a memory controller coupled to the storage device to transmit one or more initialisation signals to the storage device; wherein the storage device is to initialise the storage portion over a clock cycle in response to the one or more initialisation signals.

Abstract: A method and apparatus for transferring data maps the data to a modulation code using an encoder circuit having a configuration. A binary symbol of the data is mapped to a modulation code having a plurality of modulation digits and a modulation signal is generated based on the modulation code. A transmitter drive signal is modulated based on the modulation signal. A configuration of the encoder circuit is set based on a determined performance level. The transmitter drive signal may be used to produce an electromagnetic field by generating a positive, negative or zero electrical current in an induction coil of a first semiconductor die. A current induced by the electromagnetic field in an induction coil of a second semiconductor die is demodulated to recover the data whereby the data is transferred from the first semiconductor die to the second semiconductor die.

Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate copying of memory states between the volatile and non-volatile memory bitcells.

Abstract: The present techniques generally relate to a method of monitoring for a fault event in a lockstep processing system having a plurality of cores configured to operate in lockstep, the method having: power gating, for a period of time, a subset of cores of the plurality of cores from a first power source and providing power to the subset of cores from a second power source for the period of time; processing, at each of the cores of the plurality of cores, one or more instructions; providing an output from each core of the plurality of cores to error detection circuitry to monitor for the fault event, the output from each core based on or in response to processing the one or more instructions during the period of time.

Abstract: A method of reconfiguration and a reconfigurable circuit architecture comprising a configurable volatile storage circuit and Non-Volatile Memory circuit elements; wherein the Non-Volatile memory circuit elements store multiple bit states for re-configuration, the multiple bit states being read from the Non-Volatile memory circuit elements and written into the configurable volatile storage circuit for reconfiguration. The Non-Volatile Memory circuit elements and the configurable volatile storage circuit are provided on a common die.

Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate copying of memory states between the volatile and non-volatile memory bitcells.

Abstract: An electronic device (20) has a clock path (24) for propagating a clock signal and a clock propagating element (26) on the clock path. An analogue element (30) coupled to the clock path (24) varies, in dependence on an analogue level of a first signal (32), a switching delay for the clock propagating element (26) to trigger a transition of the clock signal. The first signal is a digitally sampled signal. This provides a mechanism for providing a fast reduction in clock frequency even if the first signal is a metastable signal, which is useful for avoiding errors causes by voltage drops.

Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, a bitcell may represent a binary value, symbol, parameter or condition based on complementary impedance states of first and second memory elements. In one aspect, a first bitline and a second bitline may be coupled to terminals of the first and second memory elements. A circuit may detect the complementary impedance states responsive to a difference in a rates of charging of the first and second bitlines.

Abstract: Examples of the present disclosure relate to a method for anomaly response in a system on chip. The method comprises measuring a magnitude of a transient anomaly event in an operating condition of the system on chip. Based on the magnitude it is determined, for each of a plurality of components of the system on chip, an indication of susceptibility of that component to an anomaly event of the measured magnitude. Based on the determined indications of susceptibility for each of the plurality of components, an anomaly response action is determined. The method then comprises performing the anomaly response action.

Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, a signal may have an amplitude within a continuous amplitude range, and a non-volatile memory element may be placed in an impedance state representing the amplitude. The amplitude of the signal may be recovered based, at least in part, on the impedance state of the correlated electron element.

Abstract: The present techniques generally relate to a method of monitoring for a fault event in a lockstep processing system having a plurality of cores configured to operate in lockstep, the method having: power gating, for a period of time, a subset of cores of the plurality of cores from a first power source and providing power to the subset of cores from a second power source for the period of time; processing, at each of the cores of the plurality of cores, one or more instructions; providing an output from each core of the plurality of cores to error detection circuitry to monitor for the fault event, the output from each core based on or in response to processing the one or more instructions during the period of time.

Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, a bitcell may represent a binary value, symbol, parameter or condition based on complementary impedance states of first and second memory elements. In one aspect, a first bitline and a second bitline may be coupled to terminals of the first and second memory elements. A circuit may detect the complementary impedance states responsive to a difference in a rates of charging of the first and second bitlines.

Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate copying of memory states between the volatile and non-volatile memory bitcells.

Abstract: A device comprises a coupling configured to couple signals to and from a communications path including at least a part of a human or animal body; a data transmitter coupled to the coupling and configured to transmit, from time to time, a data signal of at least a predetermined temporal duration via the communications path; and a data receiver coupled to the coupling and configured to detect the presence of a signal on the communications path at sets of one or more successive detection instances disposed between successive transmissions of the data signal by the data transmitter, the data receiver being configured so that the successive detection instances of a set are temporally separated by no more than the predetermined temporal duration; the device being configured to initiate a processing operation in response to a detection by the data receiver of the presence of a signal on the communications path.

Abstract: A transition detection circuit and method of operation of such a circuit are provided, the transition detection circuit having pulse generation circuitry to receive an input signal and to generate a pulse signal in response to a transition in the input signal, and pulse detection circuitry to assert an error signal on detection of the pulse signal generated by the pulse generation circuitry. The pulse generation circuitry has pulse control circuitry to control a property of the pulse signal dependent on a timing window indication signal. In particular, when the pulse signal is generated at least partly while the timing window indication signal is set, the pulse control circuitry controls the property of the pulse signal such that generated pulse signal is detected by the pulse detection circuitry.

Abstract: Subject matter disclosed herein may relate to correlated electron switch elements and, more particularly, to controlling current through correlated electron switch elements during programming operations.

Abstract: Broadly speaking, embodiments of the present techniques provide a reconfigurable hardware-based artificial neural network, wherein weights for each neural network node of the artificial neural network are obtained via training performed external to the neural network.

Abstract: Broadly speaking, the present techniques exploit the properties of correlated electron materials for artificial neural networks and neuromorphic computing. In particular, the present techniques provide apparatuses/devices that comprise at least one correlated electron switch (CES) element and which may be used as, or to form, an artificial neuron or an artificial synapse.

Abstract: A storage bitcell comprising a first inverter cross-coupled with a second inverter, both the first and second inverter being in a path between a first potential and a second potential; wherein a first isolator is connected in the path between the first inverter and the first potential. The storage bitcell has particular application as Static Random-Access Memory (SRAM) circuitry.

Abstract: Subject matter disclosed herein may relate to correlated electron switch devices, and may relate more particularly to voltage detection with correlated electron switch devices.