Patents by Inventor Shigeharu Matsushita

Shigeharu Matsushita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6901002
    Abstract: A ferroelectric memory capable of suppressing false data reading or the like by increasing a read margin is obtained. This ferroelectric memory comprises a circuit applying a read voltage VR to a first electrode and a detector capable of detecting the difference between electric capacitances Cf0 and Cf1 of a ferroelectric film when the potential difference of a second electrode corresponding to the difference between the electric capacitances Cf0 and Cf1 of the ferroelectric film is in excess of a detection limit voltage VS. The electric capacitance C2 of the second electrode is set to satisfy the following expression: Cf0<C2?½×{(Cf1?Cf0)VR/VS?(Cf1+Cf0)}.
    Type: Grant
    Filed: February 2, 2004
    Date of Patent: May 31, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Shigeharu Matsushita
  • Patent number: 6891742
    Abstract: A semiconductor memory device having a first memory including a bit line, a word line arranged to intersect with the bit line and a storage unit arranged between the bit line and the word line, and a second memory different in type from the first memory. The first memory and the second memory are formed on a semiconductor substrate in a stacked manner reducing the thickness in the height direction and attaining further miniaturization (thinning). Further, no wire having a large parasitic capacitance or solder is employed for connecting the first memory and the second memory, thereby enabling high-speed data transfer between the first memory and the second memory.
    Type: Grant
    Filed: July 12, 2002
    Date of Patent: May 10, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yoh Takano, Shigeharu Matsushita
  • Patent number: 6888189
    Abstract: A dielectric element capable of effectively suppressing diffusion of oxygen into a region located under a lower electrode in heat treatment for sintering an oxide-based dielectric film is obtained. This dielectric element comprises a lower electrode including a first conductor film having a function of suppressing diffusion of oxygen, a first dielectric film, formed on the lower electrode, including an oxide-based dielectric film, and a first insulator film, arranged on a region other than the lower electrode, having a function of suppressing diffusion of oxygen. Thus, the first conductor film and the first insulator film function as barrier films preventing diffusion of oxygen, whereby the first conductor film effectively prevents oxygen from diffusing downward along grain boundaries of the lower electrode while the first insulator film effectively prevents oxygen from diffusing downward from the region other than the lower electrode in heat treatment for sintering the oxide-based dielectric film.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: May 3, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shigeharu Matsushita, Kazunari Honma
  • Publication number: 20050068809
    Abstract: A memory capable of suppressing disturbance causing disappearance of data in a nonselected memory cell is provided. This memory comprises a memory cell array including a bit line, a word line arranged to intersect with the bit line and memory cells connected between the bit line and the word line, for accessing a selected memory cell thereby deteriorating a remanent polarization in an arbitrary memory cell and thereafter performing recovery for recovering all memory cells to remanent polarizations immediately after a write operation or remanent polarizations subjected to single application of a voltage applied to a nonselected memory cell in the access.
    Type: Application
    Filed: September 9, 2004
    Publication date: March 31, 2005
    Inventors: Toru Dan, Naofumi Sakai, Shigeharu Matsushita, Yoshiyuki Ishizuka
  • Patent number: 6816398
    Abstract: A memory device capable of improving the degree of integration and effectively preventing false data reading is obtained. This memory device comprises a pair of bit lines extending in a prescribed direction, a word line arranged to intersect with the pair of bit lines and a memory cell, arranged between the pair of bit lines and the word line, consisting of two capacitance elements. Thus, the area of the memory cell is reduced and no reference voltage is required.
    Type: Grant
    Filed: December 3, 2002
    Date of Patent: November 9, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Takeshi Sakai, Shigeharu Matsushita, Yoshiyuki Ishizuka
  • Publication number: 20040188742
    Abstract: A method of fabricating a memory capable of improving the strength of a signal read from a memory cell is provided. This method of fabricating a memory comprises steps of forming a storage part and an etched thin-film part by partially etching a storage material film formed on a first electrode film by a prescribed thickness, forming an insulator film to cover at least the thin-film part of the storage material film and patterning the insulator film and the thin-film part of the storage material film by forming an etching mask on a prescribed region of the insulator film and thereafter etching the insulator film and the thin-film part of the storage material film through the etching mask.
    Type: Application
    Filed: March 18, 2004
    Publication date: September 30, 2004
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Kazunari Honma, Shigeharu Matsushita
  • Publication number: 20040174728
    Abstract: A semiconductor memory device including different types of memories capable of attaining further miniaturization (thinning) and speed-up. This semiconductor memory device comprises a first memory including a bit line, a word line arranged to intersect with the bit line and storage means (43) arranged between the bit line and the word line and a second memory (13) different in type from the first memory. The first memory and the second memory are formed on a semiconductor substrate (31). When forming the first memory and the second memory on the same semiconductor substrate (31) in a stacked manner in this case, the thickness in the height direction is reduced, whereby further miniaturization (thinning) can be attained. Further, no wire having a large parasitic capacitance or solder may be employed for connection of the first memory and the second memory, whereby high-speed data transfer is enabled between the first memory and the second memory.
    Type: Application
    Filed: December 15, 2003
    Publication date: September 9, 2004
    Inventors: Yoh Takano, Shigeharu Matsushita
  • Patent number: 6785155
    Abstract: A ferroelectric memory capable of avoiding disturbance in non-selected cells is obtained. This ferroelectric memory comprises pulse application means for applying pulses having a prescribed pulse width causing sufficient polarization inversion when applying a high voltage to the ferroelectric capacitors while hardly causing polarization inversion when applying a low voltage to the ferroelectric capacitors to the memory cells. The ferroelectric memory applies a pulse of a high voltage having the aforementioned prescribed pulse width to a selected memory cell while applying a pulse of a low voltage having the aforementioned prescribed pulse width to non-selected memory cells in at least either data writing or data reading. Thus, writing or reading is performed on the selected memory cell, while polarization inversion is hardly caused in the non-selected memory cells. Consequently, disturbance can be avoided in the non-selected memory cells.
    Type: Grant
    Filed: April 18, 2002
    Date of Patent: August 31, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Shigeharu Matsushita
  • Publication number: 20040151019
    Abstract: A ferroelectric memory capable of suppressing false data reading or the like by increasing a read margin is obtained. This ferroelectric memory comprises a circuit applying a read voltage VR to a first electrode and a detector capable of detecting the difference between electric capacitances Cf0 and Cf1 of a ferroelectric film when the potential difference of a second electrode corresponding to the difference between the electric capacitances Cf0 and Cf1 of the ferroelectric film is in excess of a detection limit voltage VS.
    Type: Application
    Filed: February 2, 2004
    Publication date: August 5, 2004
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventor: Shigeharu Matsushita
  • Patent number: 6762476
    Abstract: A dielectric element capable of attaining excellent element characteristics by suppressing an oxide dielectric film from deterioration of characteristics caused by hydrogen is obtained. This dielectric element comprises a lower electrode including a first conductor film containing a metal, silicon and nitrogen, a first insulator film including the oxide dielectric film and an upper electrode including a second conductor film containing the metal, silicon and nitrogen, while the metal includes at least one metal selected from a group consisting of Ir, Pt, Ru, Re, Ni, Co and Mo. According to this structure, the first conductor film and the second conductor film function as barrier films preventing diffusion of hydrogen. Consequently, the first conductor film and the second conductor film suppress hydrogen from diffusing into the oxide dielectric film. Thus, the oxide dielectric film is prevented from deterioration of characteristics.
    Type: Grant
    Filed: February 1, 2002
    Date of Patent: July 13, 2004
    Assignee: Sanyo Electric Co., LTD
    Inventors: Shigeharu Matsushita, Tatsurou Gueshi
  • Patent number: 6720096
    Abstract: A dielectric element employing an oxide-based dielectric film capable of suppressing oxidation of an electrode or deterioration of film characteristics of the oxide-based dielectric film is obtained. This dielectric element comprises an insulator film including the oxide-based dielectric film and the electrode including a first conductor film containing at least a metal and silicon. The aforementioned metal includes at least one metal selected from a group consisting of Ir, Pt, Ru, Re, Ni, Co and Mo. Thus, the aforementioned first conductor film serves as a barrier film for stopping diffusion of oxygen. In heat treatment for sintering the oxide-based dielectric film, therefore, oxygen is effectively inhibited from diffusing along grain boundaries of the electrode. Consequently, a conductive material located under the electrode can be inhibited from oxidation.
    Type: Grant
    Filed: November 14, 2000
    Date of Patent: April 13, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shigeharu Matsushita, Mitsuaki Harada
  • Publication number: 20040029399
    Abstract: A dielectric device having excellent characteristics is provided. This dielectric device comprises such a first electrode layer that constituent elements located on its surface are terminated by halogen atoms and a dielectric film formed on the surface of the first electrode layer terminated by the halogen atoms. When the constituent elements for the first electrode layer located on the surface thereof are terminated by the halogen atoms in order to form a ferroelectric film having a bismuth layer structure, therefore, Bi constituting the ferroelectric film is inhibited from bonding to the constituent elements located on the surface of the first electrode layer.
    Type: Application
    Filed: August 1, 2003
    Publication date: February 12, 2004
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Kazunari Honma, Shigeharu Matsushita
  • Publication number: 20030174532
    Abstract: A ferroelectric memory capable of improving disturbance resistance in a non-selected memory cell is provided. This ferroelectric memory comprises a bit line, a word line arranged to intersect with the bit line and a diode, arranged between the bit line and the word line, including a ferroelectric capacitor and a diode serially connected to the ferroelectric capacitor. Thus, when a voltage in a range hardly feeding a current to the diode is applied to a non-selected cell in data writing or data reading, substantially no voltage is applied to the ferroelectric capacitor.
    Type: Application
    Filed: March 14, 2003
    Publication date: September 18, 2003
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Shigeharu Matsushita, Yoh Takano, Satoru Sekine
  • Patent number: 6617660
    Abstract: This invention has an objective to provide a field effect transistor semiconductor which has great adhesiveness between a gate metal and an insulating film defining a gate electrode end and to improve production yield thereof. The field effect transistor semiconductor of this invention comprises a source/drain electrode 6 positioned in a predetermined position in a GaAs substrate 1, a channel region provided in the GaAs substrate 1 and between the source/drain electrodes 6, a gate electrode 11 which is in schottky contact with a part of a channel region and is positioned between the source/drain electrodes 6, and an insulating film 7 which electrically insulates a surface of the GaAs substrate and the gate electrode 11 at both side surfaces of the gate electrode 11.
    Type: Grant
    Filed: September 8, 1999
    Date of Patent: September 9, 2003
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shigeyuki Murai, Emi Fujii, Shigeharu Matsushita, Hisaaki Tominaga
  • Publication number: 20030113985
    Abstract: This invention has an objective to provide a field effect transistor semiconductor which has great adhesiveness between a gate metal and an insulating film defining a gate electrode end and to improve production yield thereof.
    Type: Application
    Filed: September 8, 1999
    Publication date: June 19, 2003
    Inventors: SHIGEYUKI MURAI, EMI FUJII, SHIGEHARU MATSUSHITA, HISAAKI TOMINAGA
  • Publication number: 20030103374
    Abstract: A memory device capable of improving the degree of integration and effectively preventing false data reading is obtained. This memory device comprises a pair of bit lines extending in a prescribed direction, a word line arranged to intersect with the pair of bit lines and a memory cell, arranged between the pair of bit lines and the word line, consisting of two capacitance means. Thus, the area of the memory cell is reduced and no reference voltage is required.
    Type: Application
    Filed: December 3, 2002
    Publication date: June 5, 2003
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Takeshi Sakai, Shigeharu Matsushita, Yoshiyuki Ishizuka
  • Publication number: 20030103372
    Abstract: A ferroelectric memory capable of improving disturbance resistance in a non-selected cell by increasing the ratio between voltages applied to ferroelectric capacitors of a selected cell and the non-selected cell respectively is obtained. This ferroelectric memory comprises a bit line, a word line arranged to intersect with the bit line and a memory cell including a switching element arranged between the bit line and the word line and turned on with a threshold voltage having a substantially identical absolute value with respect to either of positive and negative voltage application directions and a ferroelectric capacitor arranged between the bit line and the word line and serially connected to the switching element.
    Type: Application
    Filed: November 27, 2002
    Publication date: June 5, 2003
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventor: Shigeharu Matsushita
  • Publication number: 20020154533
    Abstract: A ferroelectric memory capable of avoiding disturbance in non-selected cells is obtained. This ferroelectric memory comprises pulse application means for applying pulses having a prescribed pulse width causing sufficient polarization inversion when applying a high voltage to the ferroelectric capacitors while hardly causing polarization inversion when applying a low voltage to the ferroelectric capacitors to the memory cells. The ferroelectric memory applies a pulse of a high voltage having the aforementioned prescribed pulse width to a selected memory cell while applying a pulse of a low voltage having the aforementioned prescribed pulse width to non-selected memory cells in at least either data writing or data reading. Thus, writing or reading is performed on the selected memory cell, while polarization inversion is hardly caused in the non-selected memory cells. Consequently, disturbance can be avoided in the non-selected memory cells.
    Type: Application
    Filed: April 18, 2002
    Publication date: October 24, 2002
    Applicant: Sanyo Electric Co., Ltd.
    Inventor: Shigeharu Matsushita
  • Publication number: 20020105048
    Abstract: A dielectric element capable of attaining excellent element characteristics by suppressing an oxide dielectric film from deterioration of characteristics caused by hydrogen is obtained. This dielectric element comprises a lower electrode including a first conductor film containing a metal, silicon and nitrogen, a first insulator film including the oxide dielectric film and an upper electrode including a second conductor film containing the metal, silicon and nitrogen, while the metal includes at least one metal selected from a group consisting of Ir, Pt, Ru, Re, Ni, Co and Mo. According to this structure, the first conductor film and the second conductor film function as barrier films preventing diffusion of hydrogen. Consequently, the first conductor film and the second conductor film suppress hydrogen from diffusing into the oxide dielectric film. Thus, the oxide dielectric film is prevented from deterioration of characteristics.
    Type: Application
    Filed: February 1, 2002
    Publication date: August 8, 2002
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Shigeharu Matsushita, Tatsurou Gueshi
  • Publication number: 20020055191
    Abstract: A dielectric element capable of effectively suppressing diffusion of oxygen into a region located under a lower electrode in heat treatment for sintering an oxide-based dielectric film is obtained. This dielectric element comprises a lower electrode including a first conductor film having a function of suppressing diffusion of oxygen, a first dielectric film, formed on the lower electrode, including an oxide-based dielectric film, and a first insulator film, arranged on a region other than the lower electrode, having a function of suppressing diffusion of oxygen. Thus, the first conductor film and the first insulator film function as barrier films preventing diffusion of oxygen, whereby the first conductor film effectively prevents oxygen from diffusing downward along grain boundaries of the lower electrode while the first insulator film effectively prevents oxygen from diffusing downward from the region other than the lower electrode in heat treatment for sintering the oxide-based dielectric film.
    Type: Application
    Filed: September 21, 2001
    Publication date: May 9, 2002
    Applicant: SANYO ELECTRIC CO.,LTD.
    Inventors: Shigeharu Matsushita, Kazunari Honma