Patents by Inventor Shigeharu Matsushita

Shigeharu Matsushita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020053739
    Abstract: A semiconductor device capable of implementing a multilevel interconnection structure employing a tungsten plug after formation of a capacitor element including an oxide-based dielectric film by suppressing downward diffusion of hydrogen is obtained. This semiconductor device comprises a first interlayer dielectric film having a first opening, a first barrier film, formed at least along the inner side surface of the first opening, having a function of preventing diffusion of hydrogen, and a first conductive material embedded in the first opening through the first barrier film. Thus, the first barrier film functions as a barrier film preventing diffusion of hydrogen. Also when the tungsten plug is formed after formation of the capacitor element including the oxide-based dielectric film, therefore, the first barrier film can prevent hydrogen from diffusing into the oxide-based dielectric film.
    Type: Application
    Filed: September 14, 2001
    Publication date: May 9, 2002
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Kazunari Honma, Shigeharu Matsushita
  • Patent number: 6100547
    Abstract: A first electrode layer composed of Pt is formed on an operating layer, and a second electrode layer composed of a material which is different from Pt is formed on the operating layer so as to cover the first electrode layer. A buried electrode layer composed of Pt is formed in the operating layer under the first electrode layer. The first electrode layer, the second electrode layer and the buried electrode layer constitute a gate electrode.
    Type: Grant
    Filed: July 10, 1998
    Date of Patent: August 8, 2000
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Shigeharu Matsushita
  • Patent number: 5982023
    Abstract: A dummy gate is removed together with an SiO.sub.2 film thereon by lift-off to form a reverse dummy-gate pattern with the SiO.sub.2 film. A photoresist pattern is formed to cover the reverse dummy-gate pattern and an SiN protection film therebetween, and a mesa pattern is formed by mesa etching. The photoresist pattern is etched so that the edge of the photoresist pattern is located between the edge of the mesa pattern and the edge of the reverse dummy-gate pattern and the exposed part of the SiN protection film is etched. The edge of the SiN protection film is thus located inside the edge of the mesa pattern.
    Type: Grant
    Filed: October 15, 1997
    Date of Patent: November 9, 1999
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shigeharu Matsushita, Emi Fujii, Daijiro Inoue
  • Patent number: 5751029
    Abstract: An undoped Al.sub.0.22 Ga.sub.0.78 As layer, an undoped In.sub.0.2 Ga.sub.0.8 As electron-drifting layer, and an undoped GaAs electron-supplying layer are formed in order on a GaAs substrate. An impurity-doped layer .delta.-doped with Si donor is formed in the GaAs electron-supplying layer. An n-Al.sub.0.22 Ga.sub.0.78 As layer and n.sup.+ -GaAs cap layers are formed in order on the GaAs electron-supplying layer. A source electrode and a drain electrode are formed on the n.sup.+ -GaAs cap layers and a gate electrode is formed on the n-Al.sub.0.22 Ga.sub.0.78 As layer.
    Type: Grant
    Filed: May 17, 1996
    Date of Patent: May 12, 1998
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shigeharu Matsushita, Daijirou Inoue, Kohji Matsumura, Minoru Sawada, Yasoo Harada
  • Patent number: 5650642
    Abstract: A field effect semiconductor device comprises a first channel layer composed of an undoped semiconductor in which electrons mainly drift in low-noise operation and a second channel layer composed of a semiconductor of one conductivity type in which electrons mainly drift in high-power operation, a third channel layer being provided in the second channel layer or on the second channel layer on the opposite side of the first channel layer. The third channel layer is constituted by at least one semiconductor layer of the one conductivity type or undoped having a greater electron affinity than that of the second channel layer and having a smaller forbidden bandgap than that of the second channel layer. In another field effect semiconductor device, an undoped impurity diffusion preventing layer having an electron affinity approximately equal to that of the second channel layer is provided between the first channel layer and the second channel layer.
    Type: Grant
    Filed: March 8, 1995
    Date of Patent: July 22, 1997
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Minoru Sawada, Shigeharu Matsushita, Satoshi Terada, Emi Fujii, Yasoo Harada
  • Patent number: 5557141
    Abstract: A group III-V compound semiconductor doped with an impurity, having an undoped film of SiOx and a film for preventing the diffusion of Group V atoms (e.g., an SiN film) are formed on a crystal of Group III-V compound semiconductor in which the silicon in the SiOx film is diffused into the Group III-V compound semiconductor, thereby forming a doped layer.
    Type: Grant
    Filed: March 30, 1994
    Date of Patent: September 17, 1996
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yasoo Harada, Shigeharu Matsushita, Satoshi Terada, Emi Fujii, Takashi Kurose, Takayoshi Higashino, Takashi Yamada, Akihito Nagamatsu, Daijirou Inoue, Kouji Matsumura
  • Patent number: 5350709
    Abstract: A method of doping a Group III-V compound semiconductor with an impurity, wherein after an undoped film of SiOx and a film for preventing the diffusion of Group V atoms (e.g., an SiN film) are formed in this order on a crystal of Group III-V compound semiconductor, the sample is subjected to at least one heat treatment to cause silicon in the SiOx film to diffuse into the Group III-V compound semiconductor, thereby forming a doped layer. Using this doped layer forming method, field-effect transistors, diodes, resistive layers, two-dimensional electron gas or one-dimensional quantum wires, zero-dimensional quantum boxes, electron wave interference devices, etc. are fabricated.
    Type: Grant
    Filed: June 10, 1993
    Date of Patent: September 27, 1994
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yasoo Harada, Shigeharu Matsushita, Satoshi Terada, Emi Fujii, Takashi Kurose, Takayoshi Higashino, Takashi Yamada, Akihito Nagamatsu, Daijirou Inoue, Kouji Matsumura