Patents by Inventor Shigehiko Saida

Shigehiko Saida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7612401
    Abstract: A semiconductor device comprises a semiconductor substrate, and a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising a tunnel insulating film having a film thickness periodically and continuously changing in a channel width direction of the non-volatile memory cell, a floating gate electrode provided on the tunnel insulating film, a control gate electrode provided above the floating gate electrode, and an interelectrode insulating film provided between the control gate electrode and the floating gate electrode.
    Type: Grant
    Filed: January 25, 2006
    Date of Patent: November 3, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshio Ozawa, Shigehiko Saida, Yuji Takeuchi, Masanobu Saito
  • Patent number: 7541233
    Abstract: A semiconductor device comprises a semiconductor substrate, and a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising a tunnel insulating film having a film thickness periodically and continuously changing in a channel width direction of the non-volatile memory cell, a floating gate electrode provided on the tunnel insulating film, a control gate electrode provided above the floating gate electrode, and an interelectrode insulating film provided between the control gate electrode and the floating gate electrode.
    Type: Grant
    Filed: January 15, 2008
    Date of Patent: June 2, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshio Ozawa, Shigehiko Saida, Yuji Takeuchi, Masanobu Saito
  • Publication number: 20080119021
    Abstract: A semiconductor device comprises a semiconductor substrate, and a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising a tunnel insulating film having a film thickness periodically and continuously changing in a channel width direction of the non-volatile memory cell, a floating gate electrode provided on the tunnel insulating film, a control gate electrode provided above the floating gate electrode, and an interelectrode insulating film provided between the control gate electrode and the floating gate electrode.
    Type: Application
    Filed: January 15, 2008
    Publication date: May 22, 2008
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yoshio Ozawa, Shigehiko Saida, Yuji Takeuchi, Masanobu Saito
  • Patent number: 7372113
    Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the gate electrode and including a lower silicon nitride film containing nitrogen, silicon and hydrogen and an upper silicon nitride film formed on the lower silicon nitride film and containing nitrogen, silicon and hydrogen, and wherein a composition ratio N/Si of nitrogen (N) to silicon (Si) in the lower silicon nitride film is higher than that in the upper silicon nitride film.
    Type: Grant
    Filed: July 1, 2004
    Date of Patent: May 13, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Yoshio Ozawa, Shigehiko Saida, Akira Goda, Mitsuhiro Noguchi, Yuichiro Mitani, Yoshitaka Tsunashima
  • Publication number: 20070215958
    Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the gate electrode and including a lower silicon nitride film containing nitrogen, silicon and hydrogen and an upper silicon nitride film formed on the lower silicon nitride film and containing nitrogen, silicon and hydrogen, and wherein a composition ratio N/Si of nitrogen (N) to silicon (Si) in the lower silicon nitride film is higher than that in the upper silicon nitride film.
    Type: Application
    Filed: May 15, 2007
    Publication date: September 20, 2007
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Yoshio Ozawa, Shigehiko Saida, Akira Goda, Mitsuhiro Noguchi, Yuichiro Mitani, Yoshitaka Tsunashima
  • Patent number: 7148158
    Abstract: A semiconductor device includes a semiconductor device comprising a semiconductor substrate, source/drain regions formed in the semiconductor substrate, a gate insulation film formed on the semiconductor substrate, a gate electrode formed on the gate insulation film between the source/drain regions, and a gate sidewall spacer formed on side surfaces of the gate electrode, wherein the gate sidewall spacer is composed of silicon oxide containing 0.1–30 atomic % of chlorine.
    Type: Grant
    Filed: August 12, 2004
    Date of Patent: December 12, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshio Ozawa, Masayuki Tanaka, Kiyotaka Miyano, Shigehiko Saida
  • Patent number: 7129132
    Abstract: Hexachlorodisilane (Si2Cl6) is used as a Si raw material for forming a silicon nitride film that can be widely different in the etching rate from a silicon oxide film. The silicon nitride film is formed by an LPCVD method.
    Type: Grant
    Filed: July 21, 2004
    Date of Patent: October 31, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Shigehiko Saida, Yoshitaka Tsunashima
  • Patent number: 7098115
    Abstract: Hexachlorodisilane (Si2Cl6) is used as a Si raw material for forming a silicon nitride film that can be widely different in the etching rate from a silicon oxide film. The silicon nitride film is formed by an LPCVD method.
    Type: Grant
    Filed: July 21, 2004
    Date of Patent: August 29, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Shigehiko Saida, Yoshitaka Tsunashima
  • Patent number: 7081386
    Abstract: A semiconductor device comprises a semiconductor substrate, and a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising a tunnel insulating film having a film thickness periodically and continuously changing in a channel width direction of the non-volatile memory cell, a floating gate electrode provided on the tunnel insulating film, a control gate electrode provided above the floating gate electrode, and an interelectrode insulating film provided between the control gate electrode and the floating gate electrode.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: July 25, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshio Ozawa, Shigehiko Saida, Yuji Takeuchi, Masanobu Saito
  • Publication number: 20060141701
    Abstract: A semiconductor device having a trench capacitor is disclosed. The trench is formed on the surface of a semiconductor substrate. A first insulating film is formed on the side wall of the trench and a semiconductor film is buried in the trench. The first insulating film and the semiconductor film located in the upper part of the trench are etched and a second insulating film is deposited on the exposed side wall. The semiconductor film and the first insulating film are etched and a plate electrode is formed on the exposed side wall. A capacitor insulating film is formed on the plate electrode and a storage electrode is buried within the trench. The structure provides a semiconductor device having fewer memory cell defects.
    Type: Application
    Filed: February 23, 2006
    Publication date: June 29, 2006
    Inventors: Shigehiko Saida, Kiyotaka Miyano, Takashi Nakao
  • Publication number: 20060131641
    Abstract: A semiconductor device comprises a semiconductor substrate, and a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising a tunnel insulating film having a film thickness periodically and continuously changing in a channel width direction of the non-volatile memory cell, a floating gate electrode provided on the tunnel insulating film, a control gate electrode provided above the floating gate electrode, and an interelectrode insulating film provided between the control gate electrode and the floating gate electrode.
    Type: Application
    Filed: January 25, 2006
    Publication date: June 22, 2006
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yoshio Ozawa, Shigehiko Saida, Yuji Takeuchi, Masanobu Saito
  • Patent number: 7060555
    Abstract: Hexachlorodisilane (Si2Cl6) is used as a Si raw material for forming a silicon nitride film that can be widely different in the etching rate from a silicon oxide film. The silicon nitride film is formed by an LPCVD method.
    Type: Grant
    Filed: July 21, 2004
    Date of Patent: June 13, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Shigehiko Saida, Yoshitaka Tsunashima
  • Patent number: 6992020
    Abstract: A semiconductor device of this invention includes a silicon nitride film formed on a semiconductor substrate and having a density of 2.2 g/cm3 or less, and a silicon oxide film formed on the silicon nitride film in an ambient atmosphere containing TEOS and O3.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: January 31, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Susumu Hiyama, Akihito Yamamoto, Hiroshi Akahori, Shigehiko Saida
  • Patent number: 6903422
    Abstract: A semiconductor integrated circuit is disclosed, which includes a semiconductor substrate, a memory cell formed on the semiconductor substrate and having a first gate insulating layer of a stacked structure which includes a silicon nitride layer to become a charge storage layer, and a transistor formed on the semiconductor substrate and having a second gate insulating layer. Here, source and drain diffused layers of the memory cell are covered with a part of the first gate insulating layer, and metal silicide layers are formed on surfaces of source and drain diffused layers of the transistor.
    Type: Grant
    Filed: July 1, 2003
    Date of Patent: June 7, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Goda, Mitsuhiro Noguchi, Masayuki Tanaka, Shigehiko Saida
  • Publication number: 20050012171
    Abstract: A semiconductor device of this invention includes a silicon nitride film formed on a semiconductor substrate and having a density of 2.2 g/cm3 or less, and a silicon oxide film formed on the silicon nitride film in an ambient atmosphere containing TEOS and O3.
    Type: Application
    Filed: July 30, 2004
    Publication date: January 20, 2005
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Susumu Hiyama, Akihito Yamamoto, Hiroshi Akahori, Shigehiko Saida
  • Publication number: 20050014354
    Abstract: A semiconductor device includes a semiconductor device comprising a semiconductor substrate, source/drain regions formed in the semiconductor substrate, a gate insulation film formed on the semiconductor substrate, a gate electrode formed on the gate insulation film between the source/drain regions, and a gate sidewall spacer formed on side surfaces of the gate electrode, wherein the gate sidewall spacer is composed of silicon oxide containing 0.1-30 atomic % of chlorine.
    Type: Application
    Filed: August 12, 2004
    Publication date: January 20, 2005
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yoshio Ozawa, Masayuki Tanaka, Kiyotaka Miyano, Shigehiko Saida
  • Publication number: 20050006686
    Abstract: A semiconductor device having a trench capacitor is disclosed. The trench is formed on the surface of a semiconductor substrate. A first insulating film is formed on the side wall of the trench and a semiconductor film is buried in the trench. The first insulating film and the semiconductor film located in the upper part of the trench are etched and a second insulating film is deposited on the exposed side wall. The semiconductor film and the first insulating film are etched and a plate electrode is formed on the exposed side wall. A capacitor insulating film is formed on the plate electrode and a storage electrode is buried within the trench. The structure provides a semiconductor device having fewer memory cell defects.
    Type: Application
    Filed: February 4, 2004
    Publication date: January 13, 2005
    Inventors: Shigehiko Saida, Kiyotaka Miyano, Takashi Nakao
  • Patent number: 6841850
    Abstract: A semiconductor device of this invention includes a silicon nitride film formed on a semiconductor substrate and having a density of 2.2 g/cm3 or less, and a silicon oxide film formed on the silicon nitride film in an ambient atmosphere containing TEOS and O3.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: January 11, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Susumu Hiyama, Akihito Yamamoto, Hiroshi Akahori, Shigehiko Saida
  • Publication number: 20040266176
    Abstract: Hexachlorodisilane (Si2Cl6) is used as a Si raw material for forming a silicon nitride film that can be widely different in the etching rate from a silicon oxide film. The silicon nitride film is formed by an LPCVD method.
    Type: Application
    Filed: July 21, 2004
    Publication date: December 30, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Shigehiko Saida, Yoshitaka Tsunashima
  • Patent number: RE46122
    Abstract: Hexachlorodisilane (Si2Cl6) is used as a Si raw material for forming a silicon nitride film that can be widely different in the etching rate from a silicon oxide film. The silicon nitride film is formed by an LPCVD method.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: August 23, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masayuki Tanaka, Shigehiko Saida, Yoshitaka Tsunashima