Patents by Inventor Shigehiko Saida

Shigehiko Saida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6326658
    Abstract: A buried strap is formed after forming an SiC layer on the side surface of a trench in order to suppress the epitaxial growth of Si from the side surface (single crystal Si) of the trench to the buried strap (polycrystalline Si) without causing an increase in the contact resistance in the post process accompanied by high temperature after formation of the buried strap.
    Type: Grant
    Filed: September 24, 1999
    Date of Patent: December 4, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshitaka Tsunashima, Katsuya Okumura, Masayuki Tanaka, Shigehiko Saida, Hirofumi Inoue, Takeshi Hamamoto
  • Publication number: 20010024867
    Abstract: A semiconductor device comprises a semiconductor substrate and a silicon nitride film formed on the semiconductor substrate. The silicon nitride film is substantially free from an Si—H bond and has an Si—H density per unit area of 1×1015 cm−2 or less.
    Type: Application
    Filed: June 6, 2001
    Publication date: September 27, 2001
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shigehiko Saida, Yoshitaka Tsunashima
  • Patent number: 6284583
    Abstract: A semiconductor device comprises a semiconductor substrate and a silicon nitride film formed on the semiconductor substrate. The silicon nitride film is substantially free from an Si—H bond and has an Si—H density per unit area of 1×1015 cm−2 or less.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: September 4, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigehiko Saida, Yoshitaka Tsunashima
  • Patent number: 6146938
    Abstract: A native film formed on the surface of a silicon substrate is removed. Arsenic is doped into the surface of the silicon substrate to form an n-type impurity diffusion layer as a lower capacitor electrode. A silicon nitride film as a capacitor insulating film is formed on the n-type impurity diffusion layer without growing any oxide film on the surface of the n-type impurity diffusion layer. An upper capacitor electrode is formed on the silicon nitride film.
    Type: Grant
    Filed: June 28, 1999
    Date of Patent: November 14, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigehiko Saida, Yoshitaka Tsunashima, Tsutomu Sato
  • Patent number: 5949102
    Abstract: A semiconductor device comprises a semiconductor substrate, and a plurality of semiconductor elements provided on the semiconductor substrate. Each of the semiconductor elements includes a gate dielectric film formed on the semiconductor substrate, a gate electrode formed on the semiconductor substrate with the gate dielectric film interposed therebetween, and having a pair of side surfaces, and source/drain regions formed in a surface of the semiconductor substrate along the pair of the side surfaces. The gate electrode contains a plurality of crystal grains, and the number of the crystal grains is substantially equal to the number of crystal grains contained in any other gate electrode of all the semiconductor elements.
    Type: Grant
    Filed: June 10, 1997
    Date of Patent: September 7, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigehiko Saida, Yoshio Ozawa
  • Patent number: 5869858
    Abstract: A semiconductor device comprises a substrate, a first conductive layer formed on the substrate and comprising a first layer and a second layer formed on the first layer and having at least one of a convex and a concave, an insulating layer formed on the one of the convex and the concave of the first conductive layer, and a second conductive layer formed opposed to the one of the convex and the concave with the insulating layer interposed therebetween to thereby form a capacitive element with the first conductive layer, the insulating layer having a first region having a first capacitance value per unit area that substantially determines the capacitance value of the capacitive element and a second region having a second capacitance value per unit area that is smaller than the first capacitance value per unit area of the first region, and the second region being formed on the first layer of the conductive layer which is exposed to the one of the convex and the concave.
    Type: Grant
    Filed: March 13, 1996
    Date of Patent: February 9, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshio Ozawa, Shigehiko Saida
  • Patent number: 5866930
    Abstract: A semiconductor device comprises a first conducting layer, a first insulating layer formed on the first conducting layer, a second conducting layer formed on the first insulating layer and facing the first conducting layer, wherein, at least part of a peripheral portion of the region of at least one of the first and second conducting layers, in contact with the first insulating layer, includes an amorphous conducting layer made of a semiconductor, and the amorphous conducting layer contains at least one element selected from the group consisting of oxygen, nitrogen, carbon, argon, chlorine, and fluorine and a total concentration of the at least one element falls within the range from 0.1 atomic % to 20 atomic %.
    Type: Grant
    Filed: August 23, 1996
    Date of Patent: February 2, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigehiko Saida, Yoshio Ozawa