Patents by Inventor Shigehiko Saida

Shigehiko Saida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040266177
    Abstract: Hexachlorodisilane (Si2Cl6) is used as a Si raw material for forming a silicon nitride film that can be widely different in the etching rate from a silicon oxide film. The silicon nitride film is formed by an LPCVD method.
    Type: Application
    Filed: July 21, 2004
    Publication date: December 30, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Shigehiko Saida, Yoshitaka Tsunashima
  • Publication number: 20040256660
    Abstract: A semiconductor device comprises a semiconductor substrate, and a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising a tunnel insulating film having a film thickness periodically and continuously changing in a channel width direction of the non-volatile memory cell, a floating gate electrode provided on the tunnel insulating film, a control gate electrode provided above the floating gate electrode, and an interelectrode insulating film provided between the control gate electrode and the floating gate electrode.
    Type: Application
    Filed: March 31, 2004
    Publication date: December 23, 2004
    Inventors: Yoshio Ozawa, Shigehiko Saida, Yuji Takeuchi, Masanobu Saito
  • Publication number: 20040259386
    Abstract: Hexachlorodisilane (Si2Cl6) is used as a Si raw material for forming a silicon nitride film that can be widely different in the etching rate from a silicon oxide film. The silicon nitride film is formed by an LPCVD method.
    Type: Application
    Filed: July 21, 2004
    Publication date: December 23, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Shigehiko Saida, Yoshitaka Tsunashima
  • Publication number: 20040251521
    Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the gate electrode and including a lower silicon nitride film containing nitrogen, silicon and hydrogen and an upper silicon nitride film formed on the lower silicon nitride film and containing nitrogen, silicon and hydrogen, and wherein a composition ratio N/Si of nitrogen (N) to silicon (Si) in the lower silicon nitride film is higher than that in the upper silicon nitride film.
    Type: Application
    Filed: July 1, 2004
    Publication date: December 16, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masayuki Tanaka, Yoshio Ozawa, Shigehiko Saida, Akira Goda, Mitsuhiro Noguchi, Yuichiro Mitani, Yoshitaka Tsunashima
  • Patent number: 6794713
    Abstract: SiGe or SiC films are selectively grown on source/drain regions, followed by selectively growing silicon. A monocrystalline film having a high dislocation density or a polycrystalline film can be grown in growing the silicon film by making the C or Ge concentration higher than a predetermined level. The silicon layer on each of the source/drain regions is not monocrystalline or, even if monocrystalline, has a high density of dislocation. Therefore, the silicon film formed thereon is in the form of a monocrystalline silicon film having a high dislocation density or a polycrystalline silicon film. It is possible to suppress an impurity diffusion to reach a deep region caused by channeling of ions generated in the doping step by means of an ion implantation.
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: September 21, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Mizushima, Shigehiko Saida, Takeo Furuhata, Yoshitaka Tsunashima
  • Patent number: 6790723
    Abstract: Hexachlorodisilane (Si2Cl6) is used as a Si raw material for forming a silicon nitride film that can be widely different in the etching rate from a silicon oxide film. The silicon nitride film is formed by an LPCVD method.
    Type: Grant
    Filed: October 30, 2001
    Date of Patent: September 14, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Shigehiko Saida, Yoshitaka Tsunashima
  • Patent number: 6774462
    Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the gate electrode and including a lower silicon nitride film containing nitrogen, silicon and hydrogen and an upper silicon nitride film formed on the lower silicon nitride film and containing nitrogen, silicon and hydrogen, and wherein a composition ratio N/Si of nitrogen (N) to silicon (Si) in the lower silicon nitride film is higher than that in the upper silicon nitride film.
    Type: Grant
    Filed: October 24, 2002
    Date of Patent: August 10, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Yoshio Ozawa, Shigehiko Saida, Akira Goda, Mitsuhiro Noguchi, Yuichiro Mitani, Yoshitaka Tsunashima
  • Patent number: 6772045
    Abstract: A system for determining dry cleaning timing, includes: a manufacturing apparatus configured to process materials assigned by a sequence of lots; an apparatus controller configured to control the manufacturing apparatus and obtaining operational conditions of the manufacturing apparatus as apparatus information; a lot information input terminal configured to obtain process conditions of one of the lots as lot information; an apparatus information storage unit configured to store the apparatus information from the apparatus controller as an apparatus information database; a lot information storage unit configured to store the lot information from the lot information input terminal as a lot information database; and a cleaning determination unit configured to determine timing to perform a dry cleaning of the manufacturing apparatus based on the apparatus information database and the lot information database.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: August 3, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shuji Katsui, Masayuki Tanaka, Masaki Kamimura, Hiroshi Akahori, Ichiro Mizushima, Takashi Nakao, Akihito Yamamoto, Shigehiko Saida, Yoshitaka Tsunashima, Yuuichi Mikata
  • Publication number: 20040071030
    Abstract: A semiconductor integrated circuit is disclosed, which includes a semiconductor substrate, a memory cell formed on the semiconductor substrate and having a first gate insulating layer of a stacked structure which includes a silicon nitride layer to become a charge storage layer, and a transistor formed on the semiconductor substrate and having a second gate insulating layer. Here, source and drain diffused layers of the memory cell are covered with a part of the first gate insulating layer, and metal silicide layers are formed on surfaces of source and drain diffused layers of the transistor.
    Type: Application
    Filed: July 1, 2003
    Publication date: April 15, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akira Goda, Mitsuhiro Noguchi, Masayuki Tanaka, Shigehiko Saida
  • Patent number: 6713359
    Abstract: SiGe or SiC films are selectively grown on source/drain regions, followed by selectively growing silicon. A monocrystalline film having a high dislocation density or a polycrystalline film can be grown in growing the silicon film by making the C or Ge concentration higher than a predetermined level. The silicon layer on each of the source/drain regions is not monocrystalline or, even if monocrystalline, has a high density of dislocation. Therefore, the silicon film formed thereon is in the form of a monocrystalline silicon film having a high dislocation density or a polycrystalline silicon film. It is possible to suppress an impurity diffusion to reach a deep region caused by channeling of ions generated in the doping step by means of an ion implantation.
    Type: Grant
    Filed: May 4, 2000
    Date of Patent: March 30, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Mizushima, Shigehiko Saida, Takeo Furuhata, Yoshitaka Tsunashima
  • Publication number: 20040041179
    Abstract: SiGe or SiC films are selectively grown on source/drain regions, followed by selectively growing silicon. A monocrystalline film having a high dislocation density or a polycrystalline film can be grown in growing the silicon film by making the C or Ge concentration higher than a predetermined level. The silicon layer on each of the source/drain regions is not monocrystalline or, even if monocrystalline, has a high density of dislocation. Therefore, the silicon film formed thereon is in the form of a monocrystalline silicon film having a high dislocation density or a polycrystalline silicon film. It is possible to suppress an impurity diffusion to reach a deep region caused by channeling of ions generated in the doping step by means of an ion implantation.
    Type: Application
    Filed: September 5, 2003
    Publication date: March 4, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ichiro Mizushima, Shigehiko Saida, Takeo Furuhata, Yoshitaka Tsunashima
  • Publication number: 20040007765
    Abstract: A semiconductor device of this invention includes a silicon nitride film formed on a semiconductor substrate and having a density of 2.2 g/cm3 or less, and a silicon oxide film formed on the silicon nitride film in an ambient atmosphere containing TEOS and O3.
    Type: Application
    Filed: September 6, 2002
    Publication date: January 15, 2004
    Inventors: Susumu Hiyama, Akihito Yamamoto, Hiroshi Akahori, Shigehiko Saida
  • Publication number: 20030222318
    Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the gate electrode and including a lower silicon nitride film containing nitrogen, silicon and hydrogen and an upper silicon nitride film formed on the lower silicon nitride film and containing nitrogen, silicon and hydrogen, and wherein a composition ratio N/Si of nitrogen (N) to silicon (Si) in the lower silicon nitride film is higher than that in the upper silicon nitride film.
    Type: Application
    Filed: October 24, 2002
    Publication date: December 4, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masayuki Tanaka, Yoshio Ozawa, Shigehiko Saida, Akira Goda, Mitsuhiro Noguchi, Yuichiro Mitani, Yoshitaka Tsunashima
  • Publication number: 20030139835
    Abstract: A system for determining dry cleaning timing, includes: a manufacturing apparatus configured to process materials assigned by a sequence of lots; an apparatus controller configured to control the manufacturing apparatus and obtaining operational conditions of the manufacturing apparatus as apparatus information; a lot information input terminal configured to obtain process conditions of one of the lots as lot information; an apparatus information storage unit configured to store the apparatus information from the apparatus controller as an apparatus information database; a lot information storage unit configured to store the lot information from the lot information input terminal as a lot information database; and a cleaning determination unit configured to determine timing to perform a dry cleaning of the manufacturing apparatus based on the apparatus information database and the lot information database.
    Type: Application
    Filed: August 30, 2002
    Publication date: July 24, 2003
    Inventors: Shuji Katsui, Masayuki Tanaka, Masaki Kamimura, Hiroshi Akahori, Ichiro Mizushima, Takashi Nakao, Akihito Yamamoto, Shigehiko Saida, Yoshitaka Tsunashima, Yuuichi Mikata
  • Publication number: 20030127695
    Abstract: A semiconductor device includes a semiconductor device comprising a semiconductor substrate, source/drain regions formed in the semiconductor substrate, a gate insulation film formed on the semiconductor substrate, a gate electrode formed on the gate insulation film between the source/drain regions, and a gate sidewall spacer formed on side surfaces of the gate electrode, wherein the gate sidewall spacer is composed of silicon oxide containing 0.1-30 atomic % of chlorine.
    Type: Application
    Filed: January 8, 2003
    Publication date: July 10, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshio Ozawa, Masayuki Tanaka, Kiyotaka Miyano, Shigehiko Saida
  • Patent number: 6538271
    Abstract: A semiconductor device comprises a semiconductor substrate and a silicon nitride film formed on the semiconductor substrate. The silicon nitride film is substantially free from an Si—H bond and has an Si—H density per unit area of 1×1015 cm−2 or less.
    Type: Grant
    Filed: June 6, 2001
    Date of Patent: March 25, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigehiko Saida, Yoshitaka Tsunashima
  • Publication number: 20030042558
    Abstract: A memory cell which allows information to be written or erased electrically. The memory cell includes a gate insulation film including three layers, i.e., a first insulation layer, an electric charge accumulating layer and a second insulation layer and a gate electrode formed on the gate insulation film. The electric charge accumulating layer is composed of a silicon nitride film or silicon oxynitride film. The first and second insulation layers are composed of a silicon oxide film or silicon oxynitride film containing more oxygen composition than the electric charge accumulating layer. The thickness of the second insulation layer is more than 5 nm. The gate electrode is formed of a p-type semiconductor containing p-type impurity.
    Type: Application
    Filed: August 29, 2002
    Publication date: March 6, 2003
    Inventors: Mitsuhiro Noguchi, Akira Goda, Shigehiko Saida, Masayuki Tanaka
  • Publication number: 20020024082
    Abstract: A buried strap is formed after forming an SiC layer on the side surface of a trench in order to suppress the epitaxial growth of Si from the side surface (single crystal Si) of the trench to the buried strap (polycrystalline Si) without causing an increase in the contact resistance in the post process accompanied by high temperature after formation of the buried strap.
    Type: Application
    Filed: October 26, 2001
    Publication date: February 28, 2002
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yoshitaka Tsunashima, Katsuya Okumura, Masayuki Tanaka, Shigehiko Saida, Hirofumi Inoue, Takeshi Hamamoto
  • Publication number: 20020024119
    Abstract: Hexachlorodisilane (Si2Cl6) is used as a Si raw material for forming a silicon nitride film that can be widely different in the etching rate from a silicon oxide film. The silicon nitride film is formed by an LPCVD method.
    Type: Application
    Filed: October 30, 2001
    Publication date: February 28, 2002
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Shigehiko Saida, Yoshitaka Tsunashima
  • Patent number: 6333547
    Abstract: Hexachlorodisilane (Si2Cl6) is used as a Si raw material for forming a silicon nitride film that can be widely different in the etching rate from a silicon oxide film. The silicon nitride film is formed by an LPCVD method.
    Type: Grant
    Filed: January 6, 2000
    Date of Patent: December 25, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Shigehiko Saida, Yoshitaka Tsunashima