Patents by Inventor Shigehiro Asano

Shigehiro Asano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11960719
    Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.
    Type: Grant
    Filed: October 27, 2022
    Date of Patent: April 16, 2024
    Assignee: Kioxia Corporation
    Inventors: Hirokuni Yano, Shinichi Kanno, Toshikatsu Hida, Hidenori Matsuzaki, Kazuya Kitsunai, Shigehiro Asano
  • Publication number: 20240018516
    Abstract: A single-stranded antisense oligonucleotide, or a pharmaceutically acceptable salt thereof, capable of modulating expression and/or function of RPS25 gene, wherein nucleotides of the single-stranded antisense oligonucleotide are bonded to each other via a phosphate group and/or a modified phosphate group, the single-stranded antisense oligonucleotide includes a gap region, a 3? wing region bonded to a 3? end of the gap region, and a 5? wing region bonded to a 5? end of the gap region, the gap region is a deoxyribose-based nucleic acid optionally including a nucleic acid having a modified sugar moiety, each of the 3? wing region and the 5? wing region is a modified nucleotide, the single-stranded antisense oligonucleotide has a base length of 12- to 30-mer, and a base sequence of the antisense oligonucleotide is: a base sequence with a sequence identity of 90% to 100% to a base sequence complementary to at least one target region of the same base length as the antisense oligonucleotide present in the base sequ
    Type: Application
    Filed: November 5, 2021
    Publication date: January 18, 2024
    Applicants: Sumitomo Pharma Co., Ltd., Luxna Biotech Co., Ltd.
    Inventors: Rika Suzuki, Shigehiro Asano, Mitsumasa Kurita, Takao Suzuki, Masaki Yamagami, Ajaya Ram Shrestha, Takaaki Kawanobe, Tadashi Umemoto
  • Patent number: 11847037
    Abstract: Example implementations include a method of receiving a host command identifier associated with a host command, determining a device command associated with the host command and a memory controller device, receiving a device command timestamp corresponding to a time of the determining the device command, and determining a debug record contemporaneously with the determining the device command, the debug record including the host command identifier, a device command identifier associated with the device command, and the device command timestamp.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: December 19, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Paul Edward Hanham, Shigehiro Asano, Julien Margetts
  • Publication number: 20230297624
    Abstract: A computer-implemented method, comprising the steps of analyzing a group of content items to determine a corresponding vector representation for each content item in the group of content items, the corresponding vector representation comprising a set of identifiers representing the corresponding content item in the group of content items; receiving, a search specification; identifying a relevant initial subset of content items in the group of content items; calculating a centroid vector; analyzing the corresponding vector representations of at least a portion of content items in the group of content items to determine relative relevancies of the at least the portion of content items in the group of content items; and providing an interactive graphical visualization of at least a segment of the relevant initial subset of content items in the group of content items and one or more other content items in the group of content items.
    Type: Application
    Filed: March 13, 2023
    Publication date: September 21, 2023
    Applicant: Sumitomo Pharma Co., Ltd.
    Inventors: Shigehiro ASANO, Yoann MAMY RANDRIAMIHAJA, Mingzhe TAO
  • Publication number: 20230267075
    Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.
    Type: Application
    Filed: May 2, 2023
    Publication date: August 24, 2023
    Applicant: KIOXIA CORPORATION
    Inventors: Kazuhiro FUKUTOMI, Kenichiro YOSHII, Shinichi KANNO, Shigehiro ASANO
  • Patent number: 11727998
    Abstract: A memory system comprises a nonvolatile memory having a plurality of memory cells and a memory controller for controlling the nonvolatile memory. The plurality of memory cells is divided into different groups, and each group is assigned a threshold read count value from a predetermined range of read count values. The memory controller includes a counter which tracks a read count for each group, a determination circuit configured to compare the read count for each group tracked by the counter to the assigned threshold read count value for the group, and a nonvolatile memory read/write circuit configured to read data from the group when the determination circuit indicates the read count for the group has reached the assigned threshold read count value.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: August 15, 2023
    Assignee: Kioxia Corporation
    Inventors: Shigehiro Asano, Neil Buxton, Julien Margetts, Shunichi Igahara, Takehiko Amaki
  • Patent number: 11675697
    Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.
    Type: Grant
    Filed: February 1, 2022
    Date of Patent: June 13, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Kazuhiro Fukutomi, Kenichiro Yoshii, Shinichi Kanno, Shigehiro Asano
  • Publication number: 20230094952
    Abstract: An object of the present invention is to provide a method for culturing one or more hematopoietic stem cells applicable to hematopoietic stem cell transplantation, and a method for producing such one or more hematopoietic stem cells.
    Type: Application
    Filed: December 25, 2020
    Publication date: March 30, 2023
    Applicants: Sumitomo Pharma Co., Ltd., NextGeM Inc.
    Inventors: Atsushi Nakane, Hidetaka Nagata, Shigehiro Asano, Masanori Miyanishi, Hitoshi Suda, Yusuke Shioda
  • Publication number: 20230042619
    Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.
    Type: Application
    Filed: October 27, 2022
    Publication date: February 9, 2023
    Applicant: Kioxia Corporation
    Inventors: Hirokuni YANO, Shinichi KANNO, Toshikatsu HIDA, Hidenori MATSUZAKI, Kazuya KITSUNAI, Shigehiro ASANO
  • Patent number: 11513682
    Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: November 29, 2022
    Assignee: Kioxia Corporation
    Inventors: Hirokuni Yano, Shinichi Kanno, Toshikatsu Hida, Hidenori Matsuzaki, Kazuya Kitsunai, Shigehiro Asano
  • Patent number: 11513683
    Abstract: A data storage device capable of namespace re-sizing comprises a nonvolatile semiconductor storage device containing data accessed via a logical address that includes a namespace identifier and a logical block address, and a controller. The storage device can convert the namespace identifier to a base address using a first look up table. The storage device can further convert the logical block address to namespace allocation units of storage. The storage device can also determine a pointer using the base address, the namespace allocation units, and a second look up table. Further, the storage device can determine a full logical cluster address using the pointer.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: November 29, 2022
    Assignee: Kioxia Corporation
    Inventors: Shigehiro Asano, Julien Margetts, Philip David Rose
  • Patent number: 11482294
    Abstract: A method of managing errors in a plurality of storage drives includes receiving, at a memory controller coupled to at least one storage medium in an SSD, a read command from a host interface. The method also includes retrieving, from the storage medium, read data corresponding to a plurality of data chunks to be retrieved in response to the read command, and determining that at least one data chunk of the plurality of data chunks is unable to be read, the at least one data chunk corresponding to a failed data chunk. And in response to determining the failed data chunk, sending to the host interface the read data including the failed data chunk or excluding the failed data chunk. And in response to the read command sending to the host interface status information about all data chunks.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: October 25, 2022
    Assignee: Kioxia Corporation
    Inventors: Neil Buxton, Shigehiro Asano, Steven Wells, Mark Carlson
  • Patent number: 11372753
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller selects, as a write mode, at least one of a first mode in which N-bit data is written per memory cell in the nonvolatile memory and a second mode in which M-bit data is written per memory cell in the nonvolatile memory as a write mode. N is equal to or larger than one. M is larger than N. The controller selects the second mode when a reception speed of data, which is received in accordance with acceptance of one or more write commands from the host, is equal to or slower than a threshold, and selects the first mode when the reception speed is faster than the threshold.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: June 28, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Shigehiro Asano
  • Publication number: 20220156182
    Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.
    Type: Application
    Filed: February 1, 2022
    Publication date: May 19, 2022
    Applicant: KIOXIA CORPORATION
    Inventors: Kazuhiro FUKUTOMI, Kenichiro YOSHII, Shinichi KANNO, Shigehiro ASANO
  • Patent number: 11301373
    Abstract: A storage device includes a nonvolatile memory including a plurality of physical blocks, a communication interface connectable to a host, and a controller. The controller is configured to generate metadata of host data, which include user data and metadata of the user data, and write, in a physical block of the nonvolatile memory, the metadata of the host data, the metadata of the user data, and the user data continuously in this order, when the host data are received through the communication interface in association with a write command.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: April 12, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Daisuke Hashimoto, Shigehiro Asano, Katsuhiko Ueki, Mark Hayashida
  • Publication number: 20220083442
    Abstract: Example implementations include a method of receiving a host command identifier associated with a host command, determining a device command associated with the host command and a memory controller device, receiving a device command timestamp corresponding to a time of the determining the device command, and determining a debug record contemporaneously with the determining the device command, the debug record including the host command identifier, a device command identifier associated with the device command, and the device command timestamp.
    Type: Application
    Filed: September 16, 2020
    Publication date: March 17, 2022
    Applicant: Toshiba Memory Corporation
    Inventors: Paul Edward HANHAM, Shigehiro ASANO, Julien MARGETTS
  • Patent number: 11269766
    Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: March 8, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Kazuhiro Fukutomi, Kenichiro Yoshii, Shinichi Kanno, Shigehiro Asano
  • Publication number: 20220051736
    Abstract: A memory system comprises a nonvolatile memory having a plurality of memory cells and a memory controller for controlling the nonvolatile memory. The plurality of memory cells is divided into different groups, and each group is assigned a threshold read count value from a predetermined range of read count values. The memory controller includes a counter which tracks a read count for each group, a determination circuit configured to compare the read count for each group tracked by the counter to the assigned threshold read count value for the group, and a nonvolatile memory read/write circuit configured to read data from the group when the determination circuit indicates the read count for the group has reached the assigned threshold read count value.
    Type: Application
    Filed: October 27, 2021
    Publication date: February 17, 2022
    Inventors: Shigehiro ASANO, Neil Buxton, Julien Margetts, Shunichi Igahara, Takehiko Amaki
  • Patent number: 11189353
    Abstract: A memory system comprises a nonvolatile memory having a plurality of memory cells and a memory controller for controlling the nonvolatile memory. The plurality of memory cells is divided into different groups, and each group is assigned a threshold read count value from a predetermined range of read count values. The memory controller includes a counter which tracks a read count for each group, a determination circuit configured to compare the read count for each group tracked by the counter to the assigned threshold read count value for the group, and a nonvolatile memory read/write circuit configured to read data from the group when the determination circuit indicates the read count for the group has reached the assigned threshold read count value.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: November 30, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shigehiro Asano, Neil Buxton, Julien Margetts, Shunichi Igahara, Takehiko Amaki
  • Publication number: 20210287756
    Abstract: A method of managing errors in a plurality of storage drives includes receiving, at a memory controller coupled to at least one storage medium in an SSD, a read command from a host interface. The method also includes retrieving, from the storage medium, read data corresponding to a plurality of data chunks to be retrieved in response to the read command, and determining that at least one data chunk of the plurality of data chunks is unable to be read, the at least one data chunk corresponding to a failed data chunk. And in response to determining the failed data chunk, sending to the host interface the read data including the failed data chunk or excluding the failed data chunk. And in response to the read command sending to the host interface status information about all data chunks.
    Type: Application
    Filed: June 1, 2021
    Publication date: September 16, 2021
    Inventors: Neil Buxton, Shigehiro Asano, Steven Wells, Mark Carlson