Patents by Inventor Shigehiro Asano

Shigehiro Asano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11049581
    Abstract: A method of managing errors in a plurality of storage drives includes receiving, at a memory controller coupled to at least one storage medium in an SSD, a read command from a host interface. The method also includes retrieving, from the storage medium, read data corresponding to a plurality of data chunks to be retrieved in response to the read command, and determining that at least one data chunk of the plurality of data chunks is unable to be read, the at least one data chunk corresponding to a failed data chunk. And in response to determining the failed data chunk, sending to the host interface the read data including the failed data chunk or excluding the failed data chunk. And in response to the read command sending to the host interface status information about all data chunks.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: June 29, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Neil Buxton, Shigehiro Asano, Steven Wells, Mark Carlson
  • Publication number: 20210089209
    Abstract: A data storage device capable of namespace re-sizing comprises a nonvolatile semiconductor storage device containing data accessed via a logical address that includes a namespace identifier and a logical block address, and a controller. The storage device can convert the namespace identifier to a base address using a first look up table. The storage device can further convert the logical block address to namespace allocation units of storage. The storage device can also determine a pointer using the base address, the namespace allocation units, and a second look up table. Further, the storage device can determine a full logical cluster address using the pointer.
    Type: Application
    Filed: December 4, 2020
    Publication date: March 25, 2021
    Inventors: Shigehiro Asano, Julien Margetts, Philip David Rose
  • Publication number: 20210081315
    Abstract: A storage device includes a nonvolatile memory including a plurality of physical blocks, a communication interface connectable to a host, and a controller. The controller is configured to generate metadata of host data, which include user data and metadata of the user data, and write, in a physical block of the nonvolatile memory, the metadata of the host data, the metadata of the user data, and the user data continuously in this order, when the host data are received through the communication interface in association with a write command.
    Type: Application
    Filed: November 30, 2020
    Publication date: March 18, 2021
    Inventors: Daisuke HASHIMOTO, Shigehiro ASANO, Katsuhiko UEKI, Mark HAYASHIDA
  • Publication number: 20210042034
    Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.
    Type: Application
    Filed: October 29, 2020
    Publication date: February 11, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Hirokuni YANO, Shinichi KANNO, Toshikatsu HIDA, Hidenori MATSUZAKI, Kazuya KITSUNAI, Shigehiro ASANO
  • Publication number: 20210020253
    Abstract: A memory system comprises a nonvolatile memory having a plurality of memory cells and a memory controller for controlling the nonvolatile memory. The plurality of memory cells is divided into different groups, and each group is assigned a threshold read count value from a predetermined range of read count values. The memory controller includes a counter which tracks a read count for each group, a determination circuit configured to compare the read count for each group tracked by the counter to the assigned threshold read count value for the group, and a nonvolatile memory read/write circuit configured to read data from the group when the determination circuit indicates the read count for the group has reached the assigned threshold read count value.
    Type: Application
    Filed: October 1, 2020
    Publication date: January 21, 2021
    Inventors: Shigehiro ASANO, Neil BUXTON, Julien MARGETTS, Shunichi IGAHARA, Takehiko AMAKI
  • Patent number: 10866732
    Abstract: A data storage device capable of namespace re-sizing comprises a nonvolatile semiconductor storage device containing data accessed via a logical address that includes a namespace identifier and a logical block address, and a controller. The storage device can convert the namespace identifier to a base address using a first look up table. The storage device can further convert the logical block address to namespace allocation units of storage. The storage device can also determine a pointer using the base address, the namespace allocation units, and a second look up table. Further, the storage device can determine a full logical cluster address using the pointer.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: December 15, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Shigehiro Asano, Julien Margetts, Philip David Rose
  • Publication number: 20200379901
    Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.
    Type: Application
    Filed: August 17, 2020
    Publication date: December 3, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Kazuhiro FUKUTOMI, Kenichiro YOSHII, Shinichi KANNO, Shigehiro ASANO
  • Patent number: 10853321
    Abstract: A storage system includes non-volatile storage devices and a control device. Each of the storage devices is divided into blocks, and data is erased in units of the blocks. The control device includes a setting unit and a writing/reading unit. The setting unit sets first storage regions obtained by dividing a storage region for each of the storage devices and sets second storage regions obtained by dividing storage regions of all of the storage devices for all of the storage devices. The writing/reading unit manages data stored in the storage devices in units of the second storage regions. The setting unit sets each of the first storage regions so that the first storage region for at least one of the plurality of storage devices includes the entirety of one or more blocks and sets each of the second storage regions to include two or more of the first storage regions.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: December 1, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yohei Hasegawa, Yoshiki Saito, Shohei Onishi, Hidenori Matsuzaki, Shigehiro Asano
  • Patent number: 10854302
    Abstract: A memory system comprises a nonvolatile memory having a plurality of memory cells and a memory controller for controlling the nonvolatile memory. The plurality of memory cells is divided into different groups, and each group is assigned a threshold read count value from a predetermined range of read count values. The memory controller includes a counter which tracks a read count for each group, a determination circuit configured to compare the read count for each group tracked by the counter to the assigned threshold read count value for the group, and a nonvolatile memory read/write circuit configured to read data from the group when the determination circuit indicates the read count for the group has reached the assigned threshold read count value.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: December 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shigehiro Asano, Neil Buxton, Julien Margetts, Shunichi Igahara, Takehiko Amaki
  • Patent number: 10853233
    Abstract: A storage device includes a nonvolatile memory including a plurality of physical blocks, a communication interface connectable to a host, and a controller. The controller is configured to generate metadata of host data, which include user data and metadata of the user data, and write, in a physical block of the nonvolatile memory, the metadata of the host data, the metadata of the user data, and the user data continuously in this order, when the host data are received through the communication interface in association with a write command.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: December 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Daisuke Hashimoto, Shigehiro Asano, Katsuhiko Ueki, Mark Hayashida
  • Patent number: 10845992
    Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: November 24, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Hirokuni Yano, Shinichi Kanno, Toshikatsu Hida, Hidenori Matsuzaki, Kazuya Kitsunai, Shigehiro Asano
  • Publication number: 20200303029
    Abstract: A method of managing errors in a plurality of storage drives includes receiving, at a memory controller coupled to at least one storage medium in an SSD, a read command from a host interface. The method also includes retrieving, from the storage medium, read data corresponding to a plurality of data chunks to be retrieved in response to the read command, and determining that at least one data chunk of the plurality of data chunks is unable to be read, the at least one data chunk corresponding to a failed data chunk. And in response to determining the failed data chunk, sending to the host interface the read data including the failed data chunk or excluding the failed data chunk. And in response to the read command sending to the host interface status information about all data chunks.
    Type: Application
    Filed: March 6, 2020
    Publication date: September 24, 2020
    Inventors: Neil Buxton, Shigehiro Asano, Steven Wells, Mark Carlson
  • Patent number: 10783072
    Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: September 22, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Kazuhiro Fukutomi, Kenichiro Yoshii, Shinichi Kanno, Shigehiro Asano
  • Patent number: 10668260
    Abstract: The present invention provides a microneedle patch which can solve the problem that microneedle production is difficult and requires high accuracy, the problem that time and mental burdens on a health professional and a patient are large, and the problem caused by compounding a plurality of drugs. The microneedle patch comprises a large number of drug-carrying microprojections 4 erected on one support sheet, each microprojection 4 having a drug layer 5 soluble in vivo at its top part and having an intermediate layer 6 under the drug layer 5, the intermediate layer 6 containing a polymeric substance for adhesion of the drug layer 5 to the support sheet, the drug layer 5 at the top part of the microprojection 4 containing a single drug, the microprojections 4 holding difference types of drugs being arranged together on the support sheet 2.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: June 2, 2020
    Assignee: TAKEDA PHARMACEUTICAL COMPANY LIMITED
    Inventors: Yoshihiro Omachi, Yasuhiro Hiraishi, Masami Kusaka, Shigehiro Asano, Masao Nagao
  • Publication number: 20200105359
    Abstract: A method of managing errors in a plurality of storage drives includes receiving, at a memory controller coupled to at least one storage medium in an SSD, a read command from a host interface. The method also includes retrieving, from the storage medium, read data corresponding to a plurality of data chunks to be retrieved in response to the read command, and determining that at least one data chunk of the plurality of data chunks is unable to be read, the at least one data chunk corresponding to a failed data chunk. And in response to determining the failed data chunk, sending to the host interface the read data including the failed data chunk or excluding the failed data chunk. And in response to the read command sending to the host interface status information about all data chunks.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Neil Buxton, Shigehiro Asano, Steven Wells, Mark Carlson
  • Patent number: 10607712
    Abstract: A method of managing errors in a plurality of storage drives includes receiving, at a memory controller coupled to at least one storage medium in an SSD, a read command from a host interface. The method also includes retrieving, from the storage medium, read data corresponding to a plurality of data chunks to be retrieved in response to the read command, and determining that at least one data chunk of the plurality of data chunks is unable to be read, the at least one data chunk corresponding to a failed data chunk. And in response to determining the failed data chunk, sending to the host interface the read data including the failed data chunk or excluding the failed data chunk. And in response to the read command sending to the host interface status information about all data chunks.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: March 31, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Neil Buxton, Shigehiro Asano, Steven Wells, Mark Carlson
  • Publication number: 20200073795
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller selects, as a write mode, at least one of a first mode in which N-bit data is written per memory cell in the nonvolatile memory and a second mode in which M-bit data is written per memory cell in the nonvolatile memory as a write mode. N is equal to or larger than one. M is larger than N. The controller selects the second mode when a reception speed of data, which is received in accordance with acceptance of one or more write commands from the host, is equal to or slower than a threshold, and selects the first mode when the reception speed is faster than the threshold.
    Type: Application
    Filed: June 6, 2019
    Publication date: March 5, 2020
    Applicant: Toshiba Memory Corporation
    Inventor: Shigehiro Asano
  • Patent number: 10528464
    Abstract: A memory system includes a nonvolatile memory having memory dies controlled in parallel and each including a plurality of physical blocks, and a controller. The controller manages a plurality of logical areas for storing data portions received from the host and parities calculated from the data portions, the logical areas including first and second logical areas for storing first and second parity groups, respectively. Each first parity group includes k data portions received from the host and m parities calculated therefrom. Each second parity group includes k? data portions received from the host and m? parities calculated therefrom. Also, the controller maps each logical area to storage locations in the non-volatile memory dies such that the data portions and the parities of any one parity group are each stored in a different physical block in a set of physical blocks selected from different non-volatile memory dies.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: January 7, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Masahiro Ishiyama, Shigehiro Asano
  • Publication number: 20190287632
    Abstract: A memory system comprises a nonvolatile memory having a plurality of memory cells and a memory controller for controlling the nonvolatile memory. The plurality of memory cells is divided into different groups, and each group is assigned a threshold read count value from a predetermined range of read count values. The memory controller includes a counter which tracks a read count for each group, a determination circuit configured to compare the read count for each group tracked by the counter to the assigned threshold read count value for the group, and a nonvolatile memory read/write circuit configured to read data from the group when the determination circuit indicates the read count for the group has reached the assigned threshold read count value.
    Type: Application
    Filed: October 12, 2018
    Publication date: September 19, 2019
    Inventors: Shigehiro ASANO, Neil BUXTON, Julien MARGETTS, Shunichi IGAHARA, Takehiko AMAKI
  • Patent number: 10366003
    Abstract: According to an embodiment, a controller is connected to an external storage device and controls access to a semiconductor storage device including blocks each including memory cell groups each having memory cells. The block includes pages associated with each memory cell group. A writing process for each memory cell group includes writing stages. The controller includes a determining unit configured to determine data to be transferred to the page required in the writing process for a first memory cell group before the writing stage first starts when the writing stage is performed; a reading unit configured to read the determined data from the semiconductor storage device and to store the read data in the external storage device before the writing stage starts; and a writing unit configured to perform the writing process using the data stored in the external storage device when the writing stage is performed.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: July 30, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuhiro Fukutomi, Shinichi Kanno, Shigehiro Asano