Patents by Inventor Shigehiro Asano
Shigehiro Asano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150347020Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.Type: ApplicationFiled: August 10, 2015Publication date: December 3, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Hirokuni YANO, Shinichi Kanno, Toshikatsu Hida, Hidenori Matsuzaki, Kazuya Kitsunai, Shigehiro Asano
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Patent number: 9165685Abstract: According to one embodiment, a semiconductor memory device includes semiconductor memory chips in which data requested to be written. The data has one or more pieces of first data in a predetermined unit. The device includes a write controller that writes the first data and redundancy information calculated by using a predetermined number of pieces of the first data and used for correcting an error in the predetermined number of pieces of the first data into different semiconductor memory chips; and a storage unit that stores identification information and region specifying information so as to be associated with each other. The identification information associates the first data and the redundancy information, and the region specifying information specifies a plurality of storage regions in the semiconductor memory chips to which the pieces of the first data and the redundancy information associated with each other are written.Type: GrantFiled: June 24, 2014Date of Patent: October 20, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Shigehiro Asano, Kenichiro Yoshii, Kazuhiro Fukutomi, Shinichi Kanno
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Patent number: 9136020Abstract: According to one embodiment, a semiconductor memory device includes semiconductor memory chips in which data requested to be written. The data has one or more pieces of first data in a predetermined unit. The device includes a write controller that writes the first data and redundancy information calculated by using a predetermined number of pieces of the first data and used for correcting an error in the predetermined number of pieces of the first data into different semiconductor memory chips; and a storage unit that stores identification information and region specifying information so as to be associated with each other. The identification information associates the first data and the redundancy information, and the region specifying information specifies a plurality of storage regions in the semiconductor memory chips to which the pieces of the first data and the redundancy information associated with each other are written.Type: GrantFiled: June 24, 2014Date of Patent: September 15, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Shigehiro Asano, Kenichiro Yoshii, Kazuhiro Fukutomi, Shinichi Kanno
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Patent number: 9134924Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.Type: GrantFiled: May 20, 2014Date of Patent: September 15, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Hirokuni Yano, Shinichi Kanno, Toshikatsu Hida, Hidenori Matsuzaki, Kazuya Kitsunai, Shigehiro Asano
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Patent number: 9043564Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit, and a controller. The controller performs data transfer, stores management information including a storage position of the data stored in the second storing unit into the first storing unit, and performs data management while updating the management information. The second storing unit has a management information storage area for storing management information storage information including management information in a latest state and a storage position of the management information. The storage position information is read by the controller during a startup operation of the memory system and includes a second pointer indicating a storage position of management information in a latest state in the management information storage area and a first pointer indicating a storage position of the second pointer.Type: GrantFiled: March 26, 2014Date of Patent: May 26, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda, Shigehiro Asano, Shinichi Kanno, Toshikatsu Hida
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Patent number: 9037947Abstract: A method of controlling a nonvolatile semiconductor memory includes checking a first group at a first interval period, the first group including a plurality of blocks, and when a first block in the first group satisfies a first condition, assigning the first block to a second group. The method includes checking, at a second interval period, an error count of data stored in the second group, and when a second block in the second group satisfies a second condition, moving data stored in the second block to an erased block in which stored data is erased among the plurality of blocks.Type: GrantFiled: June 19, 2014Date of Patent: May 19, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Toshikatsu Hida, Shinichi Kanno, Hirokuni Yano, Kazuya Kitsunai, Shigehiro Asano, Junji Yano
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Patent number: 9009425Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit, and a controller. The controller performs data transfer, stores management information including a storage position of the data stored in the second storing unit into the first storing unit, and performs data management while updating the management information. The second storing unit has a management information storage area for storing management information storage information including management information in a latest state and a storage position of the management information. The storage position information is read by the controller during a startup operation of the memory system and includes a second pointer indicating a storage position of management information in a latest state in the management information storage area and a first pointer indicating a storage position of the second pointer.Type: GrantFiled: March 26, 2014Date of Patent: April 14, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda, Shigehiro Asano, Shinichi Kanno, Toshikatsu Hida
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Publication number: 20150052417Abstract: According to an embodiment, a memory system includes multiple nonvolatile memories to/from each of which data can be written/read independently of one another; and a controller configured to control writing of data to and reading of data from the nonvolatile memories. Each of the nonvolatile memories includes a data storage including a normal data storage area for storing the data and a redundant data storage area for writing the data avoiding defect positions in the normal data storage area; and a defect information storage configured to store defect information indicating information on a defect of the data storage included in another nonvolatile memory different from the present nonvolatile memory.Type: ApplicationFiled: August 14, 2014Publication date: February 19, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Yohei HASEGAWA, Shigehiro Asano, Tokumasa Hara
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Patent number: 8937844Abstract: An apparatus according to an embodiment comprises a first storage, a second storage, an input unit, a shift number determining unit, and an output unit. The first storage stores identification information of sectors and defective information indicating a presence of defect on the data line, while associating the identification information and the defective information. The second storage has storage regions in a number larger than the first number. The input unit inputs data to the second storage by the first number at a time. The shift number determining unit determines a shift number. The output unit outputs the data stored in the storage regions which is after a head storage region by the shift number, as the data is to be supplied to the data line having no defect sector based upon the defective information, and outputs information that differs from the data to the defective data line.Type: GrantFiled: February 28, 2012Date of Patent: January 20, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Shigehiro Asano, Toshikatsu Hida
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Publication number: 20140310575Abstract: According to one embodiment, a semiconductor memory device includes semiconductor memory chips in which data requested to be written. The data has one or more pieces of first data in a predetermined unit. The device includes a write controller that writes the first data and redundancy information calculated by using a predetermined number of pieces of the first data and used for correcting an error in the predetermined number of pieces of the first data into different semiconductor memory chips; and a storage unit that stores identification information and region specifying information so as to be associated with each other. The identification information associates the first data and the redundancy information, and the region specifying information specifies a plurality of storage regions in the semiconductor memory chips to which the pieces of the first data and the redundancy information associated with each other are written.Type: ApplicationFiled: June 24, 2014Publication date: October 16, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shigehiro ASANO, Kenichiro YOSHII, Kazuhiro FUKUTOMI, Shinichi KANNO
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Publication number: 20140310576Abstract: According to one embodiment, a semiconductor memory device includes semiconductor memory chips in which data requested to be written. The data has one or more pieces of first data in a predetermined unit. The device includes a write controller that writes the first data and redundancy information calculated by using a predetermined number of pieces of the first data and used for correcting an error in the predetermined number of pieces of the first data into different semiconductor memory chips; and a storage unit that stores identification information and region specifying information so as to be associated with each other. The identification information associates the first data and the redundancy information, and the region specifying information specifies a plurality of storage regions in the semiconductor memory chips to which the pieces of the first data and the redundancy information associated with each other are written.Type: ApplicationFiled: June 24, 2014Publication date: October 16, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shigehiro ASANO, Kenichiro YOSHII, Kazuhiro FUKUTOMI, Shinichi KANNO
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Publication number: 20140304567Abstract: A method of controlling a nonvolatile semiconductor memory includes checking a first group at a first interval period, the first group including a plurality of blocks, and when a first block in the first group satisfies a first condition, assigning the first block to a second group. The method includes checking, at a second interval period, an error count of data stored in the second group, and when a second block in the second group satisfies a second condition, moving data stored in the second block to an erased block in which stored data is erased among the plurality of blocks.Type: ApplicationFiled: June 19, 2014Publication date: October 9, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Toshikatsu HIDA, Shinichi KANNO, Hirokuni YANO, Kazuya KITSUNAI, Shigehiro ASANO, Junji YANO
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Publication number: 20140258602Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.Type: ApplicationFiled: May 20, 2014Publication date: September 11, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hirokuni YANO, Shinichi KANNO, Toshikatsu Hida, Hidenori MATSUZAKI, Kazuya KITSUNAI, Shigehiro ASANO
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Patent number: 8812774Abstract: According to an embodiment, a memory system includes semiconductor memories each having a plurality of blocks; a first table; a receiving unit; a generating unit; a second table; and a writing unit. The first table includes a plurality of memory areas each associated with each block and in each of which defect information is stored. The generating unit generates a set of blocks by selecting one block to which data are to be written in each semiconductor memory based on an index number indicating one of a plurality of rows in the first table and the first table. In the second table, an index number and a channel number are stored for each logical block address in association with one another. When a write command is received by the receiving unit, the writing unit writes data to a block associated with a selected channel number among blocks constituting the set.Type: GrantFiled: August 25, 2011Date of Patent: August 19, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Shigehiro Asano, Shinichi Kanno, Kazuhiro Fukutomi, Akira Yamaga
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Patent number: 8793555Abstract: A method of controlling a nonvolatile semiconductor memory includes checking, at a first interval period, an error count of data stored in a first group, the first group including a plurality of blocks/units, and when a first block/unit in the first group satisfies a first condition, assigning the first block/unit to a second group. The method includes checking, at a second interval period, an error count of data stored in the second group, the second interval period being shorter than the first interval period, and when a second block/unit in the second group satisfies a second condition, moving data stored in the second block/unit to an erased block/unit in which stored data is erased among the plurality of blocks/units.Type: GrantFiled: October 9, 2013Date of Patent: July 29, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Toshikatsu Hida, Shinichi Kanno, Hirokuni Yano, Kazuya Kitsunai, Shigehiro Asano, Junji Yano
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Publication number: 20140208013Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit, and a controller. The controller performs data transfer, stores management information including a storage position of the data stored in the second storing unit into the first storing unit, and performs data management while updating the management information. The second storing unit has a management information storage area for storing management information storage information including management information in a latest state and a storage position of the management information. The storage position information is read by the controller during a startup operation of the memory system and includes a second pointer indicating a storage position of management information in a latest state in the management information storage area and a first pointer indicating a storage position of the second pointer.Type: ApplicationFiled: March 26, 2014Publication date: July 24, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Junji YANO, Hidenori MATSUZAKI, Kosuke HATSUDA, Shigehiro ASANO, Shinichi KANNO, Toshikatsu HIDA
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Patent number: 8788900Abstract: According to one embodiment, a semiconductor memory device includes semiconductor memory chips in which data requested to be written. The data has one or more pieces of first data in a predetermined unit. The device includes a write controller that writes the first data and redundancy information calculated by using a predetermined number of pieces of the first data and used for correcting an error in the predetermined number of pieces of the first data into different semiconductor memory chips; and a storage unit that stores identification information and region specifying information so as to be associated with each other. The identification information associates the first data and the redundancy information, and the region specifying information specifies a plurality of storage regions in the semiconductor memory chips to which the pieces of the first data and the redundancy information associated with each other are written.Type: GrantFiled: April 23, 2013Date of Patent: July 22, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Shigehiro Asano, Kenichiro Yoshii, Kazuhiro Fukutomi, Shinichi Kanno
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Patent number: 8782331Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.Type: GrantFiled: August 9, 2012Date of Patent: July 15, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hirokuni Yano, Shinichi Kanno, Hida Toshikatsu, Hidenori Matsuzaki, Kazuya Kitsunai, Shigehiro Asano
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Patent number: 8738867Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit, and a controller. The controller performs data transfer, stores management information including a storage position of data stored in the second storing unit into the first storing unit, and performs data management while updating the management information. The second storing unit stores management information in a latest state and a storage position of the management information. The storage position information is read by the controller during a startup operation of the memory system and includes a second pointer indicating a storage position of the management information in a latest state and a first pointer indicating a storage position of the second pointer. The first pointer is stored in a fixed area in the second storing unit and the second pointer is stored in an area excluding the fixed area in the second storing unit.Type: GrantFiled: April 2, 2013Date of Patent: May 27, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda, Shigehiro Asano, Shinichi Kanno, Toshikatsu Hida
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Patent number: 8719615Abstract: A semiconductor device performs operation in synchronization with a certain clock signal. The semiconductor device includes a control unit for outputting operation control information, a storage unit for storing data, a first operation unit for performing operation on first data in accordance with first operation control information, and a second operation unit for performing operation on second data in accordance with second operation control information. The first operation unit includes a plurality of operation circuits. The number of logic gates constituting the entire operation circuits is m. The second operation unit includes at least one operation circuit in which the number of logic gates is n (n>m). Each of the total delay of the operation unit or the total delay of the operation unit is set at a value equal to or less than the cycle of the clock signal.Type: GrantFiled: March 17, 2011Date of Patent: May 6, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Yohei Hasegawa, Yutaka Yamada, Takashi Yoshikawa, Shigehiro Asano