Abstract: An image display device (2) controls a backlight luminance on the basis of a plurality of areas corresponding to LEDs, which are defined by dividing an input image. To cause sides of each subscreen to coincide with sides of its corresponding area, a subscreen control section (10) included in the image display device (2) changes positions and sizes of subscreen input images Dv1 to Dv3 included in a multiscreen input image Dv, the positions and the sizes being determined by subscreen setting data Ds, which is setting information. As a result, the number of areas corresponding to each subscreen is reduced, so that the number of LEDs to be lit up is reduced without causing display failures, thereby achieving low power consumption.

Abstract: Disclosed is a thin-film transistor (10) manufacturing method that includes a process for forming a nitrate film (12x) that includes residual nickel (22) on a surface thereof, by bringing a nitric acid solution into contact with a polysilicon layer (11x); and a process for removing the nitrate film (12x) that includes residual nickel (22) from the polysilicon layer (11x) surface. With this surface treatment process, a polysilicon layer (11) with reduced concentration of a surface residual nickel (22) is provided, and a thin-film transistor (10) having excellent surface smoothness is attained.

Abstract: A pn junction type solar cell is formed in a predetermined region on a substrate made of glass. Light emitted from a light emitting unit reaches an n-type semiconductor layer after it passed through substrate. The solar cell generates electromotive force corresponding to a quantity of the emitted light. A control circuit, a mask ROM, a transmitting circuit and an antenna are formed on an upper side of the solar cell. A surface of a semiconductor storage device is entirely covered with an insulating film to block entry of outside air. The insulating film is typically formed of physicochemically stable glass or silicon dioxide.

Abstract: The invention provides, in one aspect, a virtual processor that includes one or more virtual processing units. These virtual processing units execute on one or more processors, and each virtual processing unit executes one or more processes or threads (collectively, “threads”). While the threads may be constrained to executing throughout their respective lifetimes on the same virtual processing units, they need not be. The invention provides, in other aspects, virtual and/or digital data processors with improved dataflow-based synchronization. A process or thread (collectively, again, “thread”) executing within such processor can execute a memory instruction (e.g., and “Empty” or other memory-consumer instruction) that permits the thread to wait on the availability of data generated, e.g., by another thread and to transparently wake up when that other thread makes the data available (e.g., by execution of a “Fill” or other memory-producer instruction).

Abstract: The invention provides an embedded processor architecture comprising a plurality of virtual processing units that each execute processes or threads (collectively, “threads”). One or more execution units, which are shared by the processing units, execute instructions from the threads. An event delivery mechanism delivers events—such as, by way of non-limiting example, hardware interrupts, software-initiated signaling events (“software events”) and memory events—to respective threads without execution of instructions. Each event can, per aspects of the invention, be processed by the respective thread without execution of instructions outside that thread. The threads need not be constrained to execute on the same respective processing units during the lives of those threads—though, in some embodiments, they can be so constrained. The execution units execute instructions from the threads without needing to know what threads those instructions are from.

Abstract: Disclosed is a thin-film transistor (10) manufacturing method that includes a process for forming a nitrate film (12x) that includes residual nickel (22) on a surface thereof, by bringing a nitric acid solution into contact with a polysilicon layer (11x); and a process for removing the nitrate film (12x) that includes residual nickel (22) from the polysilicon layer (11x) surface. With this surface treatment process, a polysilicon layer (11) with reduced concentration of a surface residual nickel (22) is provided, and a thin-film transistor (10) having excellent surface smoothness is attained.

Abstract: Disclosed is a display device capable of changing a video image display area of high significance so as to be brighter than a video image display area of low significance, from among a plurality of video images. The display device comprises a liquid crystal display panel (1), a backlight unit (2), and a video image compositing unit (7) that generates composite video image data and backlight data. The backlight data is generated corresponding to the significance of the plurality of video images, and by the brightness of the backlight being adjusted for each display area on the basis of the backlight data, the video image display area of high significance is made brighter than the video image display area of low significance.

Abstract: An image display device (2) controls a backlight luminance on the basis of a plurality of areas corresponding to LEDs, which are defined by dividing an input image. To cause sides of each subscreen to coincide with sides of its corresponding area, a subscreen control section (10) included in the image display device (2) changes positions and sizes of subscreen input images Dv1 to Dv3 included in a multiscreen input image Dv, the positions and the sizes being determined by subscreen setting data Ds, which is setting information. As a result, the number of areas corresponding to each subscreen is reduced, so that the number of LEDs to be lit up is reduced without causing display failures, thereby achieving low power consumption.

Abstract: The invention provides an embedded processor architecture comprising a plurality of virtual processing units that each execute processes or threads (collectively, “threads”). One or more execution units, which are shared by the processing units, execute instructions from the threads. An event delivery mechanism delivers events—such as, by way of non-limiting example, hardware interrupts, software-initiated signaling events (“software events”) and memory events—to respective threads without execution of instructions. Each event can, per aspects of the invention, be processed by the respective thread without execution of instructions outside that thread. The threads need not be constrained to execute on the same respective processing units during the lives of those threads—though, in some embodiments, they can be so constrained. The execution units execute instructions from the threads without needing to know what threads those instructions are from.

Abstract: The invention provides, in one aspect, a virtual processor that includes one or more virtual processing units. These virtual processing units execute on one or more processors, and each virtual processing unit executes one or more processes or threads (collectively, “threads”). While the threads may be constrained to executing throughout their respective lifetimes on the same virtual processing units, they need not be. The invention provides, in other aspects, virtual and/or digital data processors with improved dataflow-based synchronization. A process or thread (collectively, again, “thread”) executing within such processor can execute a memory instruction (e.g., and “Empty” or other memory-consumer instruction) that permits the thread to wait on the availability of data generated, e.g., by another thread and to transparently wake up when that other thread makes the data available (e.g, by execution of a “Fill” or other memory-producer instruction).

Abstract: The invention provides, in one aspect, a virtual processor that includes one or more virtual processing units. These virtual processing units execute on one or more processors, and each virtual processing unit executes one or more processes or threads (collectively, “threads”). While the threads may be constrained to executing throughout their respective lifetimes on the same virtual processing units, they need not be. An event delivery mechanism associates events with respective threads and notifies those threads when the events occur, regardless of which virtual processing unit and/or processor the threads happen to be executing on at the time. The invention provides, in other aspects, virtual and/or digital data processors with improved dataflow-based synchronization. A process or thread (collectively, again, “thread”) executing within such processor can execute a memory instruction (e.g.

Abstract: In a manufacturing method of a thin film transistor (1), the oxide film forming step is performed whereby: a process-target substrate (2) having a surface on which a gate oxide film (4) should be formed is immersed in an oxidizing solution containing an active oxidizing species; and a gate oxide film (4) is formed through direct oxidation of polycrystalline silicon (51) on the process-target substrate (2). With this step, a silicon dioxide film (42) is formed while growing a silicon dioxide film (41) on the process-target substrate 2. Accordingly, the interface between the polycrystalline silicon (51) and the gate oxide film (4) is kept clean. The gate oxide film (4) is uniformly formed with excellent quality in insulation tolerance and other properties. Therefore, the thin film transistor (1) contains a high quality oxide film with excellent insulation tolerance and other properties which can be formed at low temperature.

Abstract: The invention provides, in one aspect, a virtual processor that includes one or more virtual processing units. These virtual processing units execute on one or more processors, and each virtual processing unit executes one or more processes or threads (collectively, “threads”). While the threads may be constrained to executing throughout their respective lifetimes on the same virtual processing units, they need not be. An event delivery mechanism associates events with respective threads and notifies those threads when the events occur, regardless of which virtual processing unit and/or processor the threads happen to be executing on at the time. The invention provides, in other aspects, virtual and/or digital data processors with improved dataflow-based synchronization. A process or thread (collectively, again, “thread”) executing withing such processor can execute a memory instruction (e.g.

Abstract: The invention provides an embedded processor architecture comprising a plurality of virtual processing units that each execute processes or threads (collectively, “threads”). One or more execution units, which are shared by the processing units, execute instructions from the threads. An event delivery mechanism delivers events—such as, by way of non-limiting example, hardware interrupts, software-initiated signaling events (“software events”) and memory events—to respective threads without execution of instructions. Each event can, per aspects of the invention, be processed by the respective thread without execution of instructions outside that thread. The threads need not be constrained to execute on the same respective processing units during the lives of those threads—though, in some embodiments, they can be so constrained. The execution units execute instructions from the threads without needing to know what threads those instructions are from.

Abstract: A pn junction type solar cell is formed in a predetermined region on a substrate made of glass. Light emitted from a light emitting unit reaches an n-type semiconductor layer after it passed through substrate. The solar cell generates electromotive force corresponding to a quantity of the emitted light. A control circuit, a mask ROM, a transmitting circuit and an antenna are formed on an upper side of the solar cell. A surface of a semiconductor storage device is entirely covered with an insulating film to block entry of outside air. The insulating film is typically formed of physicochemically stable glass or silicon dioxide.

Abstract: An object of the present invention is to provide an electronic circuit device capable of reducing the occurrence of electromagnetic waves associated with the propagation of a signal by utilizing light as a signal. The electronic circuit device has a transparent substrate (hereinafter written as a substrate) over which an optical sensor and an optical shutter and an electronic circuit composed of thin film transistors (TFTs) are formed. An optical signal is inputted from an external into the electronic circuit device, the optical signal is directly irradiated on the optical sensor over the substrate, and penetrates through the substrate, and inputted into an optical sensor over another substrate. The optical sensor converts the optical signal into an electronic signal, and the circuit over the substrate operates.

Abstract: The invention provides, in one aspect, a virtual processor that includes one or more virtual processing units. These virtual processing units execute on one or more processors, and each virtual processing unit executes one or more processes or threads (collectively, “threads”). While the threads may be constrained to executing throughout their respective lifetimes on the same virtual processing units, they need not be. An event delivery mechanism associates events with respective threads and notifies those threads when the events occur, regardless of which virtual processing unit and/or processor the threads happen to be executing on at the time. The invention provides, in other aspects, virtual and/or digital data processors with improved dataflow-based synchronization. A process or thread (collectively, again, “thread”) executing within such processor can execute a memory instruction (e.g.

Abstract: A transistor model for a simulator simulates a resistance between a source region and a drain region with a model equation which has terms representing resistance values corresponding respectively to areas of mutually different impurity concentrations below a gate section in simulating characteristics of a transistor. At least two of the terms each having a threshold parameter indicating a voltage at which a semiconductor element composed of the associated region and regions adjacent to that region changes from an ON state to an OFF state. The threshold parameters of the terms being specified independently from each other. Thus, the characteristics of a transistor having a set of areas of mutually different impurity concentrations below a gate section, inclusive of subthreshold regions which are difficult to evaluate through actual measurement, can be simulated to high accuracy while preserving a good fit with a capacitance model.

Abstract: The invention provides an embedded processor architecture comprising a plurality of virtual processing units that each execute processes or threads (collectively, “threads”). One or more execution units, which are shared by the processing units, execute instructions from the threads. An event delivery mechanism delivers events—such as, by way of non-limiting example, hardware interrupts, software-initiated signaling events (“software events”) and memory events—to respective threads without execution of instructions. Each event can, per aspects of the invention, be processed by the respective thread without execution of instructions outside that thread. The threads need not be constrained to execute on the same respective processing units during the lives of those threads—though, in some embodiments, they can be so constrained. The execution units execute instructions from the threads without needing to know what threads those instructions are from.

Abstract: The invention provides, in one aspect, a virtual processor that includes one or more virtual processing units. These virtual processing units execute on one or more processors, and each virtual processing unit executes one or more processes or threads (collectively, “threads”). While the threads may be constrained to executing throughout their respective lifetimes on the same virtual processing units, they need not be. An event delivery mechanism associates events with respective threads and notifies those threads when the events occur, regardless of which virtual processing unit and/or processor the threads happen to be executing on at the time. The invention provides, in other aspects, virtual and/or digital data processors with improved dataflow-based synchronization. A process or thread (collectively, again, “thread”) executing within such processor can execute a memory instruction (e.g.