Abstract: A voltage supply circuit has a resistive element, a p-channel MOS transistor, and n-channel MOS transistors. The resistive element and the p-channel MOS transistor are connected in parallel between a power source node and a node. The n-channel MOS transistors are connected in series between the node and the ground node. The voltage supply circuit supplies a threshold voltage of the n-channel MOS transistor to the node connected to a cell Vcc line of a memory cell in response to a test mode signal TE of the H level, and supplies an external source voltage in response to a test mode signal of the L level. In such a manner, a memory cell having an abnormal current in a standby mode can be detected by an operation test.

Abstract: A memory cell of an SRAM has a full CMOS cell structure having successively aligned three wells of different conductivity types, and includes first and second contact holes extending from positions on first and second gates to positions above an impurity region of a predetermined MOS transistor, and formed in a self-aligned fashion with respect to the first and second gates, and first and second local interconnections formed in the contact holes, respectively.

Abstract: An SRAM memory cell relating to the present invention includes: first and second access MOS transistors; first and second driver MOS transistors; and first and second load MOS transistors. An insulating layer is formed on first and second gates respectively forming gates of the first and second driver MOS transistors and gates of the first and second load MOS transistors. On the insulating layer, formed are first and second conductive layers for forming capacitances between the first and second gates and the conductive layers. Furthermore, formed are a first local interconnect connecting the first gate and the second conductive layer therebetween and a second local interconnect connecting the second gate and the first conductive layer therebetween.

Abstract: Inter power supply surge voltage transmitting diode element is formed by a buried layer formed in a semiconductor substrate, a well region formed on the buried layer with its bottom portion being in contact with the buried layer, and impurity regions of mutually different conductivity types formed apart from each other at the surface of the well region. One of the impurity regions is electrically coupled to a first power supply line on which a surge voltage generates, and the other is electrically coupled to a second power supply line absorbing the surge voltage. The surge transmitting element includes a plurality of elements arranged parallel to each other between the first and second power supply lines. The second power supply line supplies the power supply voltage to an internal circuitry which consumes relatively small current.

Abstract: This SRAM includes a P-channel MOS transistor which is provided corresponding to each row and connected between one end of the memory cell power source line of the corresponding row and the line of the power source potential and which has a comparatively high conduction resistance value, and a program circuit that lets the P-channel MOS transistor become electrically non-conducted when a fuse is cut. Therefore, electric currents are prevented from flowing to a short-circuited part of the defective memory cell MC, and the leakage electric current can be restrained to a small value even if a latch-up phenomenon is generated.

Abstract: An inverter receives a reset signal output from a reset signal generating circuit, and drives a potential level of a first internal node according to whether a fuse element is blown or not. A transfer gate is provided between the first internal node and a second internal node and drives the first internal node and the second internal node to either a conductive state or a shutdown state according to a delayed reset signal from the reset signal generating circuit. A latch circuit is provided between the second internal node and an output node, and latches a potential level of the second internal node and outputs an inverted level of the potential level of the second internal node to the output node.

Abstract: In an input buffer circuit, a second stage includes a BiNMOS non-inverter and a CMOS inverter, and a driver circuit includes BiNMOS push-pull circuits.

Abstract: In a power on reset (POR) circuit, when power is turned on, an output signal of an inverter attains an H level and an N channel MOS transistor is rendered conductive. The potential of an input node of the inverter becomes a potential of a power supply voltage divided by a conductive resistance value R1 of a P channel MOS transistor and a conductive resistance value R2 of an N channel MOS transistor. Assuming that the threshold voltage of the inverter is 0.8 V and R1:R2=2:3, then the power supply voltage Vres at the time when signal POR# inverts its level becomes 1.33 V. Thus, this POR circuit can reliably be utilized even in a product designed to operate with 1.5 V incorporating a MOS transistor having a threshold voltage of 0.8 V.

Abstract: In a semiconductor memory device having a plurality of data input/output pins, control pins (e.g. address pins and external control signal pins) are arranged parallel to each other on a chip. The plurality of data input/output pins are divided into a plurality of groups. Each group has a specific data input/output pin. The specific data input/output pin is lined up with the control pins. In a test mode, a signal is written into all memory cells by applying the signal to the specific data input/output pin. In addition, whether the signals read from all memory cells are correct or not is determined using the specific data input/output pin.

Abstract: A semiconductor memory device according to the present invention comprises, in general, a memory cell array, a plurality of first-layer and second-layer bit lines. The memory cell array includes a matrix of memory cells arranged along a line and row directions, each memory cell being formed within a memory cell region. Each of first-layer bit lines is extending along the row direction, and provided on a plurality of the memory cell regions. Each of second-layer bit lines is connected with the first-layer bit line via a connecting hole. The memory cell regions include first and second memory cell regions, the first memory cell region is provided with the connecting hole, the second memory cell region is not provided with the connecting hole. Also, at least one of the memory cells formed within the first memory cell regions is a dummy cell incapable of electrically serving as the normal memory cell.

Abstract: A semiconductor memory device according to the present invention comprises, in general, a memory cell array, a plurality of first-layer and second-layer bit lines. The memory cell array includes a matrix of memory cells arranged along a line and row directions, each memory cell being formed within a memory cell region. Each of first-layer bit lines is extending along the row direction, and provided on a plurality of the memory cell regions. Each of second-layer bit lines is connected with the first-layer bit line via a connecting hole. The memory cell regions include first and second memory cell regions, the first memory cell region is provided with the connecting hole, the second memory cell region is not provided with the connecting hole. Also, at least one of the memory cells formed within the first memory cell regions is a dummy cell incapable of electrically serving as the normal memory cell.

Abstract: At the last stage of a level converter that provides an internal signal to an internal signal output node, MOS transistors that are rendered conductive alternatively are provided as current source transistors. These additional MOS transistors are selectively rendered conductive according to the voltage level of, for example, a bonding pad. The charging/discharging current towards the internal node can be adjusted. Accordingly, the rising time and falling time of the internal signal can be constantly made equal. Thus an input/output circuit that can provide a signal at a proper timing even when the operating environment such as the system power supply voltage changes can be implemented.

Abstract: In an input buffer circuit, a second stage includes a BiNMOS non-inverter and a CMOS inverter, and a driver circuit includes BiNMOS push-pull circuits.

Abstract: In an SRAM, a line for applying an internal power supply potential to a memory cell and a line applying an external power supply potential to the portion other than memory cell are separately provided, and an N channel MOS transistor is connected between line for the internal power supply potential and a line for a ground potential. MOS transistor becomes conductive with a predetermined resistance value in a conductive state during test mode. Thus, the potential of line, which has been precharged to internal power supply potential, rapidly decreases to a down-converted potential. Therefore, reduction in time required for a hold test is achieved.

Abstract: Predetermined bits of an address signal taken into an address register are taken into a burst address counter and are changed in synchronization with a clock signal. The address bits from the burst address counter are applied to a block decoder for selecting a memory sub-array from the plurality of memory sub-arrays. A block address and the memory sub-array to be selected change at every clock cycle. An operation frequency of data read circuits provided for the respective memory sub-arrays can be made lower than a frequency of the clock signal. Memory cell data can be read out accurately even in a high-frequency operation.

Abstract: An input protection circuit device for protecting a device in a semiconductor circuit device when a surge current is applied to a signal input terminal of the semiconductor circuit device is provided. The input circuit device includes an nMOS transistor between an input signal line connecting an input pad and an internal circuit and a first power supply (Vcc), and having a gate electrode connected to GND via a resistor-C, and a diode between the input signal line and GND. When a positive surge current higher than the potential of the first power supply (Vcc) is applied to the input pad, and when a negative surge current lower than the potential of GND is applied, the surge current is moderated by the nMOS transistor and by the diode, respectively, to prevent the flow of the surge current to the internal circuit.

Abstract: A semiconductor memory device comprises a dynamic memory cell array, a static memory cell array, a plurality of word lines, a plurality of DRAM bit line pairs and a plurality of SRAM bit line pairs. The dynamic memory cell array comprises a plurality of dynamic memory cells arranged in the shape of a matrix. The static memory cell array is arranged adjacent to the dynamic memory cell array. The static memory cell array includes the static memory cells arranged in the shape of a matrix. A plurality of word lines are arranged in a plurality of rows. Each word line is connected to the dynamic and static memory cells arranged in the corresponding rows. A plurality of DRAM bit line pairs are arranged in a plurality of columns. Each DRAM bit line pair is connected to the dynamic memory cells. A plurality of SRAM bit line pairs are arranged in the other plurality of columns. Each SRAM bit line pair is connected to the static memory cells arranged in the corresponding columns.

Abstract: A checking circuit is provided which electrically and selectively connects a pad to which an internal circuit is connected, to a reference potential source node, in accordance with a potential of a special pad, when activated. The checking circuit is activated when a burn-in mode detection signal is activated. By detecting a leak current of a pin terminal to which the pad connected to the circuit is electrically connected, the potential of the special pad, that is, set internal function, can be externally identified. Accordingly, a bonding option function of which internal function is set in accordance with the potential of the bonding pad, can be externally detected in a non-destructive manner.

Abstract: A small-sized semiconductor integrated circuit is provided in which the potential of a predetermined node can be set to an intermediate potential in a short period after a power source is turned on. By using a power on reset signal which is inverted when a source potential is set to a predetermined intermediate potential, a P channel MOS transistor whose source directly receives the source potential supplies charges to the predetermined node at an early stage after the power source is turned on until the source potential reaches the intermediate potential.

Abstract: To obtain a semiconductor memory device capable of keeping the internal circuit in active state at all times, without increasing the power consumption during normal operation, and not increasing the number of pins. A burn-in clock generating circuit (1) receives an external clock CLK, a mode signal MODE, and an internal clock INTCLK to output a burn-in clock BICLK to a decoder (5). The burn-in clock BICLK becomes a signal equivalent to the internal clock INTCLK when the mode signal MODE is a fixed signal of H or L indicating normal operation, and becomes a fixed signal of H for indicating activation at all times when the mode signal MODE is a clock at half frequency of the external clock CLK.