Abstract: A power on reset circuit includes a transistor connected between a power supply node and a first node, a first capacitor connected between a ground node and a first node, a resistance element connected parallel to the first capacitor, a first CMOS inverter circuit having an input node connected to the first node and an output node connected to the second node, and a second CMOS inverter circuit having an input node connected to the second node and an output node connected to the first node. Preferably, the power on reset circuit further includes a second capacitor connected between the power supply node and the second node. In the power on reset circuit, when the power is turned off, the first capacitor is fully discharged by the resistance element. Therefore, a reset signal for initializing internal circuitry can be surely generated even when the power is again turned on.

Abstract: A double current mirror type differential amplifier that can operate at high speed is only used for a predetermined time period to amplify speedily a potential difference according to data read out from a memory cell. When the potential difference amplified by the double current mirror type differential amplifier becomes greater than an offset voltage of a latch type amplifier, the potential difference is further amplified only with the latch type amplifier of low power consumption. By providing a double current mirror type differential amplifier that can operate at high speed but has great power consumption and a latch type amplifier that has low power consumption but cannot operate at high speed, the disadvantage of the double current mirror type differential amplifier is compensated for by the latch type amplifier, and the disadvantage of the latch type amplifier is compensated for by the advantage of the double current mirror type differential amplifier.

Abstract: A synchronous semiconductor memory device includes a clock pulse generator generating internal first and second clock pulses in synchronization with an external clock signal for application, respectively, to a word line select decoder selecting a row of memory cells, and to a bit line select decoder selecting a column of memory cells, a sense amplifier sensing and amplifying a data of selected memory cell and a write driver writing a data to the selected memory cell. Word line select decoder is enabled when the first clock pulse is active, and bit line select decoder, sense amplifier and write driver are activated when the second clock pulse is active. These circuits are activated only for a necessary minimum period, and current consumption is reduced.

Abstract: A semiconductor memory device comprises a dynamic memory cell array, a static memory cell array, a plurality of word lines, a plurality of DRAM bit line pairs and a plurality of SRAM bit line pairs. The dynamic memory cell array comprises a plurality of dynamic memory cells arranged in the shape of a matrix. The static memory cell array is arranged adjacent to the dynamic memory cell array. The static memory cell array includes the static memory cells arranged in the shape of a matrix. A plurality of word lines are arranged in a plurality of rows. Each word line is connected to the dynamic and static memory cells arranged in the corresponding rows. A plurality of DRAM bit line pairs are arranged in a plurality of columns. Each DRAM bit line pair is connected to the dynamic memory cells. A plurality of SRAM bit line pairs are arranged in the other plurality of columns. Each SRAM bit line pair is connected to the static memory cells arranged in the corresponding columns.

Abstract: A delay circuit delays an internal write control signal by a prescribed time to a global write driver. The global write driver is enabled in response to the delayed write control signal received from the delay circuit, to drive a global write data bus in accordance with internal write data from an input buffer. A block write driver is enabled in response to an internal write control signal and a block selection signal, to drive a local write data bus in response to data on the global write data bus. A write gate connects a bit line to the local write data bus in response to a column selection signal. The delay circuit sets the output of the block write driver at a low level for a prescribed period, whereby a precharge potential of the bit line is reduced to reduce the potential amplitude of the bit line in data writing. An SRAM which operates at a high speed with an enlarged write recovery time margin is provided. SRAM also includes various arrangement for improving operating characteristics and reliability.

Abstract: A delay circuit delays an internal write control signal by a prescribed time to a global write driver. The global write driver is enabled in response to the delayed write control signal received from the delay circuit, to drive a global write data bus in accordance with internal write data from an input buffer. A block write driver is enabled in response to an internal write control signal and a block selection signal, to drive a local write data bus in response to data on the global write data bus. A write gate connects a bit line to the local write data bus in response to a column selection signal. The delay circuit sets the output of the block write driver at a low level for a prescribed period, whereby a precharge potential of the bit line is reduced to reduce the potential amplitude of the bit line in data writing. An SRAM which operates at a high speed with an enlarged write recovery time margin is provided. SRAM also includes various arrangement for improving operating characteristics and reliability.

Abstract: A synchronous semiconductor memory device includes a clock input circuit receiving an externally applied clock signal to produce an internal clock signal, a signal input circuit taking in an externally applied signal to produce an internal signal, a first delay circuit delaying an externally applied snooze mode signal by a first delay time for supplying to a clock input circuit, and a second delay circuit delaying the externally applied snooze mode signal by a second delay time for supplying to the signal input circuit. The clock input circuit and the signal input circuit are disabled when the internal snooze mode signal is active. The semiconductor memory device takes in the external signal and produces an internal signal in synchronization with the internal clock signal. Upon switching over to the snooze mode, the operation is performed in accordance with the external signal in the cycle in which the snooze mode is designated, and the internal operation is inhibited in the subsequent cycles.

Abstract: A semiconductor memory comprising a flip-flop circuit, a redundant memory cell row and column, a specific address detecting gate, a transistor, a sense amplifier and a data output buffer. The receipt of a supply potential causes the flip-flop circuit to generate previously stored output status representing the use or the nonuse of the redundant memory cell row and column. Upon detection of a specific address by the specific address detecting gate, the transistor effects a switching operation causing the output status generated by the flip-flop circuit to be output to the outside via the transistor, sense amplifier and data output buffer. This allows the use or the nonuse of the redundant bits to be verified efficiently.

Abstract: A delay circuit delays an internal write control signal by a prescribed time to a global write driver. The global write driver is enabled in response to the delayed write control signal received from the delay circuit, to drive a global write data bus in accordance with internal write data from an input buffer. A block write driver is enabled in response to an internal write control signal and a block selection signal, to drive a local write data bus in response to data on the global write data bus. A write gate connects a bit line to the local write data bus in response to a column selection signal. The delay circuit sets the output of the block write driver at a low level for a prescribed period, whereby a precharge potential of the bit line is reduced to reduce the potential amplitude of the bit line in data writing. An SRAM which operates at a high speed with an enlarged write recovery time margin is provided. SRAM also includes various arrangement for improving operating characteristics and reliability.

Abstract: A delay circuit delays an internal write control signal by a prescribed time to a global write driver. The global write driver is enabled in response to the delayed write control signal received from the delay circuit, to drive a global write data bus in accordance with internal write data from an input buffer. A block write driver is enabled in response to an internal write control signal and a block selection signal, to drive a local write data bus in response to data on the global write data bus. A write gate connects a bit line to the local write data bus in response to a column selection signal. The delay circuit sets the output of the block write driver at a low level for a prescribed period, whereby a precharge potential of the bit line is reduced to reduce the potential amplitude of the bit line in data writing. An SRAM which operates at a high speed with an enlarged write recovery time margin is provided. SRAM also includes various arrangement for improving operating characteristics and reliability.

Abstract: A delay circuit delays an internal write control signal by a prescribed time to a global write driver. The global write driver is enabled in response to the delayed write control signal received from the delay circuit, to drive a global write data bus in accordance with internal write data from an input buffer. A block write driver is enabled in response to an internal write control signal and a block selection signal, to drive a local write data bus in response to data on the global write data bus. A write gate connects a bit line to the local write data bus in response to a column selection signal. The delay circuit sets the output of the block write driver at a low level for a prescribed period, whereby a precharge potential of the bit line is reduced to reduce the potential amplitude of the bit line in data writing. An SRAM which operates at a high speed with an enlarged write recovery time margin is provided. SRAM also includes various arrangement for improving operating characteristics and reliability.

Abstract: A semiconductor memory device has a plurality of memory cells arranged in rows and columns, a plurality of pairs of complementary first and second bit lines arranged corresponding to respective columns and connecting memory cells on a corresponding column, first and second read data lines, and a plurality of pairs of first and second bipolar transistor provided for respective pairs of first and second bit lines. Each first bipolar transistor is coupled to the first read data line and each second bipolar transistor is coupled to the second read data line and a plurality of first switching circuits transfer potentials of the first and second bit lines to respective bases of corresponding first and second bipolar transistors. A reference line transmits a non-selection level voltage and a plurality of second switching circuits, operating complementary to the corresponding first switching circuits, transfer the non-selection level voltage to bases of corresponding first and second bipolar transistors.

Abstract: A divided word line driving circuit applicable to a static random access memory (SRAM) employing a divided word line method is disclosed. When a divided word line is activated, the potential at the input of an inverter for driving the word line is brought to a low level. When the input signals S1 and S2 are both at a low level, the divided word line is brought to an inactive state. The input of the inverter is charged by a transistor 101 in addition to a transistor 102 which is always on. In other words, transistor 101 contributes to accelerating charging of the input of the inverter. Consequently, the potential of the divided word line is made to rise at high speed, so that access operation at high speed can be achieved. The circuit is implemented with a small number of transistors, so that it becomes also possible to enhance the degree of integration of a SRAM.

Abstract: A semiconductor integrated circuit includes a plurality of emitter-coupled logic (ECL) circuits (10) and circuitry (5, 6a, 6b) generating a reference potential to determine the logic threshold value of the ECL circuits. The reference potential generating circuitry is provided near a first pad (2) for a first supply voltage (VCC) and includes a circuit (5) for generating a first reference potential from the first supply voltage, and a circuit (6a, 6b) provided one for each the group of ECL circuits and provided near an associated ECL circuit group for generating a second reference potential from the first reference potential to generate a reference potential as the logic threshold potential of a corresponding ECL circuit.

Abstract: Disclosed is a sense amplifier employing an emitter coupled logic (ECL) circuit. A constant voltage generating circuit independent of a change or a fluctuation of a power supply voltage level is provided. Two current-mirror circuits supply constant currents to the ECL circuit based on a generated constant voltage. Since a constant current independent of the change of power supply voltage level is supplied to the ECL circuit, the ECL circuit reliably converts a small potential difference generated between I/O lines into a current signal. Accordingly, no erroneous reading operation is performed.

Abstract: An ECL buffer circuit includes an input portion for receiving an input signal at an ECL level, a current switch portion and an output portion. The input portion includes a bipolar transistor (Q1), a level-shift diode (D1) and a constant current source (CS1). The current switch portion includes a first and a second switch circuits and a constant current source (CS2). Each switch circuit includes a resistor (R1, R2) and a bipolar transistor (Q2, Q3). The output portion includes a first and a second output circuits and a constant current source (CS3). Each output circuit includes an emitter follower transistor (Q4, Q5) and a bipolar transistor (Q6, Q7). The first output circuit receives an input signal from the input portion, and the second output circuit receives a reference voltage (V.sub.BB). A by-pass resistor (R3, R4) is connected between the base and the emitter of an emitter follower transistor (Q4, Q5) of each output circuit.

Abstract: An ECL buffer circuit includes an input portion for receiving an input signal at an ECL level, a current switch portion and an output portion. The input portion includes a bipolar transistor (Q1), a level-shift diode (D1) and a constant current source (CS1). The current switch portion includes a first and a second switch circuits and a constant current source (CS2). Each switch circuit includes a resistor (R1, R2) and a bipolar transistor (Q2, Q3). The output portion includes a first and a second output circuits and a constant current source (CS3). Each output circuit includes an emitter follower transistor (Q4, Q5) and a bipolar transistor (Q6, Q7). The first output circuit receives an input signal from the input portion, and the second output circuit receives a reference voltage (V.sub.BB). A by-pass resistor (R3, R4) is connected between the base and the emitter of an emitter follower transistor (Q4, Q5) of each output circuit.

Abstract: Disclosed is a sense amplifier employing an emitter coupled logic (ECL) circuit. A constant voltage generating circuit independent of a change or a fluctuation of a power supply voltage level is provided. Two current-mirror circuits supply constant currents to the ECL circuit based on a generated constant voltage. Since a constant current independent of the change of power supply voltage level is supplied to the ECL circuit, the ECL circuit reliably converts a small potential difference generated between I/O lines into a current signal. Accordingly, no erroneous reading operation is performed.

Abstract: A self-timed random-access memory device includes randomly accessible memory circuitry (7), a clock generator (9) responsive to an external clock signal for generating an internal clock signal, an input circuit (8') responsive to the internal clock signal for latching and outputting a supplied input signal, an output circuit (11') responsive to the internal clock signal for latching and outputting an output from the memory device, and circuitry (81, 82, 85, 86; 115, 116, 124, 125; 135, 136, 144, 145) responsive to a through state specifying signal (TH, THM) for disabling the latch function of the input circuit and the output circuit. The memory device can be switched, in response to the through state specifying signal, between a mode operating synchronously with the externally supplied clock signal and another mode operating asynchronously with the externally supplied clock signal.

Abstract: A Bi-CMOS logic circuit structured by bipolar transistors and insulated gate type transistors includes a first NPN bipolar transistor for charging an output node and a second NPN bipolar transistor for discharging the output node. The first bipolar transistor has a collector coupled to a first power supply and an emitter connected to the output node. The second bipolar transistor has a collector connected to the output node and an emitter coupled to a second power supply. The Bi-CMOS logic circuit also includes at least one P channel insulated gate type transistor provided between the first power supply and a base of the first bipolar transistor for receiving an input signal at its gate, and at least one N channel insulated gate type transistor provided between the output node and a base of the second bipolar transistor for receiving the input signal at its gate.