Patents by Inventor Shigeki Sakai

Shigeki Sakai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240101742
    Abstract: A living radical polymer that has a low molecular weight distribution and has a specific functional group at least at one end, and a resin-coated pigment has high dispersibility of a resin composition including the living radical polymer, is excellent in properties such as preservation stability, discharge stability, and color developability in a dispersed state, and is suitably used in a pigment dispersion. A living radical polymer has a specific functional group structure, the living radical polymer includes a polymerization initiator-derived specific organic compound moiety at one end or in a backbone of the living radical polymer and is obtained by reacting a radical generator having a specific functional group with at least any end, for example, an iodine end ascribable to a precursor. A living radical polymer composition includes the same; a resin-coated pigment is obtained by coating with the living radical polymer composition; and a method produces the living radical polymer.
    Type: Application
    Filed: January 21, 2022
    Publication date: March 28, 2024
    Applicants: NOF CORPORATION, NATIONAL UNIVERSITY CORPORATION YAMAGATA UNIVERSITY
    Inventors: Masumi TAKAMURA, Tatsuhiro TAKAHASHI, Shigeki TAKAHASHI, Shinri SAKAI
  • Patent number: 11415599
    Abstract: A contact probe may include a Ni pipe that may include a coiled spring structure, and the Ni pipe 11 may contain 0.5 to 10 wt % of phosphorus (P). The contact probe may have improved durability, by reducing shrinkage, after probing performed in a high temperature environment.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: August 16, 2022
    Assignee: NIDEC READ CORPORATION
    Inventors: Masami Yamamoto, Norihiro Ota, Shigeki Sakai
  • Patent number: 11335783
    Abstract: A FeFET and a method of its manufacture are provided, the FeFET having a ferroelectric whose film thickness (dr) is made small and so nanofine as to range in: 59 nm<dr<150 nm, without impairing the data retention property of not less than 105 seconds and the data rewrite endurance property of not less than 108 times, of those that have hitherto been developed, and the FeFET allowing a memory window of 0.40 V or more when a sweep amplitude of the gate voltage is not more than 3.3 V.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: May 17, 2022
    Assignees: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, WACOM R&D CORPORATION
    Inventors: Shigeki Sakai, Mitsue Takahashi, Masaki Kusuhara, Masayuki Toda, Masaru Umeda, Yoshikazu Sasaki
  • Patent number: 11069713
    Abstract: A semiconductor memory element is provided including a laminated structure, in which a memory member and a conductor are superposed on a semiconductor substrate. The memory member has a bottom surface in contact with the semiconductor substrate, an upper surface in contact with the conductor, and side surfaces, which are in contact with and surrounded by a partition wall; the bottom surface of the memory member has a width of equal to or not more than 100 nm; a shortest distance between the conductor and the semiconductor substrate is twice or more of the width of the bottom surface of the memory member; the side surface of the memory member has a width, which is either the same as the width of the bottom surface and constant at any position above the bottom surface, or the widest at a position other than the bottom surface and above the bottom surface.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: July 20, 2021
    Assignees: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, WACOM
    Inventors: Mitsue Takahashi, Shigeki Sakai, Masaki Kusuhara, Masayuki Toda, Masaru Umeda, Yoshikazu Sasaki
  • Publication number: 20200300930
    Abstract: A method for producing an MI element includes: an insulation step of forming an insulator layer on an outer periphery of an amorphous wire; an electroless plating step of forming an electroless plating layer on an outer peripheral surface of the insulator layer; an electrolytic plating step of forming an electrolytic plating layer on an outer peripheral surface of the electroless plating layer; a resist step of forming a resist layer on an outer peripheral surface of the electrolytic plating layer; an exposure step of exposing the resist layer with a laser to form a spiral groove strip on an outer peripheral surface of the resist layer; an etching step of performing etching using the resist layer as a masking material and removing the electroless plating layer and the electrolytic plating layer in the groove strip to form a coil with the remaining electroless plating layer and electrolytic plating layer.
    Type: Application
    Filed: November 26, 2018
    Publication date: September 24, 2020
    Inventors: Masami YAMAMOTO, Kazuhiko KITANO, Norihiro OTA, Shigeki SAKAI, Kiyoshi NUMATA
  • Patent number: 10782317
    Abstract: Provided is a contact probe which may achieve improved heat resistance even when a spring portion thereof is compressed and released in a high temperature environment. The contact probe includes an Ni—P layer, and the Ni—P layer has different concentrations of P at different positions in a thickness direction of the Ni—P layer.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: September 22, 2020
    Assignee: NIDEC-READ CORPORATION
    Inventors: Masami Yamamoto, Norihiro Ota, Shigeki Sakai
  • Publication number: 20200279927
    Abstract: [Object] To provide a FeFET and a method of its manufacture, the FeFET having a ferroelectric whose film thickness (dr) is made small and so nanofine as to range in: 59 nm<dr<150, without impairing the data retention property of not less than 105 seconds and the data rewrite withstand property of not less than 108 times, of those that have hitherto been developed, and the FeFET allowing data to be written with a writing voltage whose absolute value is not more than 3.3 volts. [Means for Solving] In methods of making a device in which an insulator, a film made of constituent elements of a bismuth layered perovskite crystalline ferroelectric and a metal are sequentially formed in the indicated order on a semiconductor substrate and thereafter are annealed for ferroelectric crystallization, thereby preparing the device composed of the semiconductor, insulator, ferroelectric and metal, a method of making a semiconductor ferroelectric memory element in which the film is composed of Ca.
    Type: Application
    Filed: May 8, 2020
    Publication date: September 3, 2020
    Inventors: Shigeki SAKAI, Mitsue TAKAHASHI, Masaki KUSUHARA, Masayuki TODA, Masaru UMEDA, Yoshikazu SASAKI
  • Patent number: 10686043
    Abstract: [Object] To provide a FeFET and a method of its manufacture, the FeFET having a ferroelectric whose film thickness (dr) is made small and so nanofine as to range in: 59 nm<dr<150, without impairing the data retention property of not less than 105 seconds and the data rewrite withstand property of not less than 108 times, of those that have hitherto been developed, and the FeFET allowing data to be written with a writing voltage whose absolute value is not more than 3.3 volts. [Means for Solving] In methods of making a device in which an insulator, a film made of constituent elements of a bismuth layered perovskite crystalline ferroelectric and a metal are sequentially formed in the indicated order on a semiconductor substrate and thereafter are annealed for ferroelectric crystallization, thereby preparing the device composed of the semiconductor, insulator, ferroelectric and metal, a method of making a semiconductor ferroelectric memory element in which the film is composed of Ca.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: June 16, 2020
    Assignees: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, WACOM R&D CORPORATION
    Inventors: Shigeki Sakai, Mitsue Takahashi, Masaki Kusuhara, Masayuki Toda, Masaru Umeda, Yoshikazu Sasaki
  • Patent number: 10600608
    Abstract: An ion source is provided. The ion source includes a plasma generation chamber, a plate member, and an extraction electrode. The plasma generation chamber is supplied with a halogen-containing material. The plate member is provided on an end of the plasma generation chamber located on a side toward which an ion beam is extracted. The extraction electrode is disposed downstream of the plate member. The plate member is formed with a gas supply passage via which hydrogen gas is supplied to the extraction electrode.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: March 24, 2020
    Assignee: NISSIN ION EQUIPMENT CO., LTD.
    Inventors: Masakazu Adachi, Shigeki Sakai, Yuya Hirai, Takayuki Murayama, Tomoya Taniguchi, Weijiang Zhao
  • Publication number: 20190383858
    Abstract: A contact probe may include a Ni pipe that may include a coiled spring structure, and the Ni pipe 11 may contain 0.5 to 10 wt % of phosphorus (P). The contact probe may have improved durability, by reducing shrinkage, after probing performed in a high temperature environment.
    Type: Application
    Filed: October 4, 2017
    Publication date: December 19, 2019
    Inventors: Masami YAMAMOTO, Norihiro OTA, Shigeki SAKAI
  • Publication number: 20190273086
    Abstract: A semiconductor memory element is provided including a laminated structure, in which a memory member and a conductor are superposed on a semiconductor substrate. The memory member has a bottom surface in contact with the semiconductor substrate, an upper surface in contact with the conductor, and side surfaces, which are in contact with and surrounded by a partition wall; the bottom surface of the memory member has a width of equal to or not more than 100 nm; a shortest distance between the conductor and the semiconductor substrate is twice or more of the width of the bottom surface of the memory member; the side surface of the memory member has a width, which is either the same as the width of the bottom surface and constant at any position above the bottom surface, or the widest at a position other than the bottom surface and above the bottom surface.
    Type: Application
    Filed: July 3, 2017
    Publication date: September 5, 2019
    Applicants: National Institute of Advanced Industrial Science and Technology, WACOM R&D Corporation
    Inventors: Mitsue TAKAHASHI, Shigeki SAKAI, Masaki KUSUHARA, Masayuki TODA, Masaru UMEDA, Yoshikazu SASAKI
  • Patent number: 10192972
    Abstract: Provided is a ferroelectric field effect transistor (FeFET) which has a wide memory window even if the ferroelectric film thickness is 200 nm or less, and which has excellent data retention characteristics, pulse rewriting endurance and the like. An FeFET which has a structure wherein an insulating body (11) and a gate electrode conductor (4) are sequentially laminated in this order on a semiconductor base (10) that has a source region (12) and a drain region (13). The insulating body (11) is configured by laminating a first insulating body (1) and a second insulating body (2) in this order on the base (10), and the second insulating body (2) is mainly composed of an oxide of strontium, calcium, bismuth and tantalum.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: January 29, 2019
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Shigeki Sakai, Wei Zhang, Mitsue Takahashi
  • Publication number: 20180340960
    Abstract: Provided is a contact probe which may achieve improved heat resistance even when a spring portion thereof is compressed and released in a high temperature environment. The contact probe includes an Ni—P layer, and the Ni—P layer has different concentrations of P at different positions in a thickness direction of the Ni—P layer.
    Type: Application
    Filed: May 25, 2018
    Publication date: November 29, 2018
    Inventors: Masami YAMAMOTO, Norihiro OTA, Shigeki SAKAI
  • Patent number: 10002751
    Abstract: An ion beam irradiation apparatus is provided. The apparatus includes an ion source, a mass separator, and an energy filter. The mass separator sorts dopant ions having a specific mass number and valence from an ion beam extracted from the ion source, and outputs the dopant ions. The energy filter is formed to define a beam passing region for allowing the ion beam to pass therethrough, and configured to have a given filter potential in response to application of a voltage thereto to separate passable ions capable of passing through the beam passing region and non-passable ions incapable of passing through the beam passing region, from each other by a difference in ion energy. The given filter potential is set such that the dopant ions are included in the passable ions, and a portion of unwanted ions which cannot be separated from the dopant ions by the mass separator are included in the non-passable ions.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: June 19, 2018
    Assignee: NISSIN ION EQUIPMENT CO., LTD.
    Inventors: Naoya Takahashi, Hideki Fujita, Yosuke Yoshimura, Shigeki Sakai
  • Publication number: 20180130909
    Abstract: A ferroelectric device and a manufacturing method are provided. While holding a nonvolatile memory retention capability and a multiple rewriting endurance as the distinctive features of a ferroelectric device, the disclosed ferroelectric device is wider in memory window and more adaptively made microfiner than a conventional ferroelectric device that has used a ferroelectric mainly constituted of Sr—Bi—Ta—O as an oxide of strontium, bismuth and tantalum. Directly on or with intermediary of an insulator on a semiconductor there are layered a first ferroelectric and a conductor to form a gate stack, the first ferroelectric being mainly constituted of Sr—Ca—Bi—Ta—O as an oxide of strontium, calcium, bismuth and tantalum and being built up by a metal organic vapor deposition technique from a suitable film-forming raw material. The gate stack is heat-treated to cause the first ferroelectric to develop its ferroelectricity.
    Type: Application
    Filed: August 11, 2017
    Publication date: May 10, 2018
    Inventors: Shigeki SAKAI, Mitsue TAKAHASHI, Masaki KUSUHARA, Masayuki TODA, Masaru UMEDA
  • Publication number: 20180006130
    Abstract: Provided is a ferroelectric field effect transistor (FeFET) which has a wide memory window even if the ferroelectric film thickness is 200 nm or less, and which has excellent data retention characteristics, pulse rewriting endurance and the like. An FeFET which has a structure wherein an insulating body (11) and a gate electrode conductor (4) are sequentially laminated in this order on a semiconductor base (10) that has a source region (12) and a drain region (13). The insulating body (11) is configured by laminating a first insulating body (1) and a second insulating body (2) in this order on the base (10), and the second insulating body (2) is mainly composed of an oxide of strontium, calcium, bismuth and tantalum.
    Type: Application
    Filed: August 29, 2017
    Publication date: January 4, 2018
    Inventors: Shigeki SAKAI, Wei ZHANG, Mitsue TAKAHASHI
  • Patent number: 9818869
    Abstract: A ferroelectric device and a manufacturing method are provided. While holding a nonvolatile memory retention capability and a multiple rewriting endurance as the distinctive features of a ferroelectric device, the disclosed ferroelectric device is wider in memory window and more adaptively made microfiner than a conventional ferroelectric device that has used a ferroelectric mainly constituted of Sr—Bi—Ta—O as an oxide of strontium, bismuth and tantalum. Directly on or with intermediary of an insulator on a semiconductor there are layered a first ferroelectric and a conductor to form a gate stack, the first ferroelectric being mainly constituted of Sr—Ca—Bi—Ta—O as an oxide of strontium, calcium, bismuth and tantalum and being built up by a metal organic vapor deposition technique from a suitable film-forming raw material. The gate stack is heat-treated to cause the first ferroelectric to develop its ferroelectricity.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: November 14, 2017
    Assignees: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, WACOM R&D CORPORATION
    Inventors: Shigeki Sakai, Mitsue Takahashi, Masaki Kusuhara, Masayuki Toda, Masaru Umeda
  • Publication number: 20170309488
    Abstract: [Object] To provide a FeFET and a method of its manufacture, the FeFET having a ferroelectric whose film thickness (dr) is made small and so nanofine as to range in: 59 nm<dr<150, without impairing the data retention property of not less than 105 seconds and the data rewrite withstand property of not less than 108 times, of those that have hitherto been developed, and the FeFET allowing data to be written with a writing voltage whose absolute value is not more than 3.3 volts. [Means for Solving] In methods of making a device in which an insulator, a film made of constituent elements of a bismuth layered perovskite crystalline ferroelectric and a metal are sequentially formed in the indicated order on a semiconductor substrate and thereafter are annealed for ferroelectric crystallization, thereby preparing the device composed of the semiconductor, insulator, ferroelectric and metal, a method of making a semiconductor ferroelectric memory element in which the film is composed of Ca.
    Type: Application
    Filed: April 21, 2017
    Publication date: October 26, 2017
    Inventors: Shigeki SAKAI, Mitsue TAKAHASHI, Masaki KUSUHARA, Masayuki TODA, Masaru UMEDA, Yoshikazu SASAKI
  • Patent number: 9780186
    Abstract: Provided is a ferroelectric field effect transistor (FeFET) which has a wide memory window even if the ferroelectric film thickness is 200 nm or less, and which has excellent data retention characteristics, pulse rewriting endurance and the like. An FeFET which has a structure wherein an insulating body (11) and a gate electrode conductor (4) are sequentially laminated in this order on a semiconductor base (10) that has a source region (12) and a drain region (13). The insulating body (11) is configured by laminating a first insulating body (1) and a second insulating body (2) in this order on the base (10), and the second insulating body (2) is mainly composed of an oxide of strontium, calcium, bismuth and tantalum.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: October 3, 2017
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Shigeki Sakai, Wei Zhang, Mitsue Takahashi
  • Publication number: 20170243730
    Abstract: An ion beam irradiation apparatus is provided. The apparatus includes an ion source, a mass separator, and an energy filter. The mass separator sorts dopant ions having a specific mass number and valence from an ion beam extracted from the ion source, and outputs the dopant ions. The energy filter is formed to define a beam passing region for allowing the ion beam to pass therethrough, and configured to have a given filter potential in response to application of a voltage thereto to separate passable ions capable of passing through the beam passing region and non-passable ions incapable of passing through the beam passing region, from each other by a difference in ion energy. The given filter potential is set such that the dopant ions are included in the passable ions, and a portion of unwanted ions which cannot be separated from the dopant ions by the mass separator are included in the non-passable ions.
    Type: Application
    Filed: October 28, 2016
    Publication date: August 24, 2017
    Applicant: NISSIN ION EQUIPMENT CO., LTD.
    Inventors: Naoya TAKAHASHI, Hideki FUJITA, Yosuke YOSHIMURA, Shigeki SAKAI