Patents by Inventor Shigeki Sakai

Shigeki Sakai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160247932
    Abstract: A ferroelectric device and a manufacturing method are provided. While holding a nonvolatile memory retention capability and a multiple rewriting endurance as the distinctive features of a ferroelectric device, the disclosed ferroelectric device is wider in memory window and more adaptively made microfiner than a conventional ferroelectric device that has used a ferroelectric mainly constituted of Sr—Bi—Ta—O as an oxide of strontium, bismuth and tantalum. Directly on or with intermediary of an insulator on a semiconductor there are layered a first ferroelectric and a conductor to form a gate stack, the first ferroelectric being mainly constituted of Sr—Ca—Bi—Ta—O as an oxide of strontium, calcium, bismuth and tantalum and being built up by a metal organic vapor deposition technique from a suitable film-forming raw material. The gate stack is heat-treated to cause the first ferroelectric to develop its ferroelectricity.
    Type: Application
    Filed: July 24, 2014
    Publication date: August 25, 2016
    Inventors: Shigeki SAKAI, Mitsue TAKAHASHI, Masaki KUSUHARA, Masayuki TODA, Masaru UMEDA
  • Publication number: 20150171183
    Abstract: Provided is a ferroelectric field effect transistor (FeFET) which has a wide memory window even if the ferroelectric film thickness is 200 nm or less, and which has excellent data retention characteristics, pulse rewriting endurance and the like. An FeFET which has a structure wherein an insulating body (11) and a gate electrode conductor (4) are sequentially laminated in this order on a semiconductor base (10) that has a source region (12) and a drain region (13). The insulating body (11) is configured by laminating a first insulating body (1) and a second insulating body (2) in this order on the base (10), and the second insulating body (2) is mainly composed of an oxide of strontium, calcium, bismuth and tantalum.
    Type: Application
    Filed: May 30, 2013
    Publication date: June 18, 2015
    Inventors: Shigeki Sakai, Wei Zhang, Mitsue Takahashi
  • Patent number: 8461548
    Abstract: To improve an efficiency of utilizing electrons and efficiently suppress an ion beam spread by a space charge effect while eliminating a need for a special magnetic pole structure by effectively using a space in the vicinity of a magnet, there are provided an ion source, a collimating magnet and a plurality of electron sources, wherein the electron sources are arranged in a magnetic field gradient region formed on an ion beam upstream side or ion beam downstream side of the collimating magnet and arranged outside a region passed by the ion beam, and an irradiation direction of the electrons is directed to supply the electrons to the magnetic field gradient region.
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: June 11, 2013
    Assignees: Nissin ION Equipment Co., Ltd., Kyoto University
    Inventors: Dan Nicolaescu, Shigeki Sakai, Junzo Ishikawa, Yasuhito Gotoh
  • Patent number: 8159873
    Abstract: There is provided a semiconductor integrated circuit including a state detection enhancement circuit which includes an input terminal and an output terminal and has a function of generating an electric potential of a magnitude capable of performing nonvolatile memory writing into a nonvolatile memory circuit based on an electric potential input to the input terminal and outputting the electric potential of the magnitude to the output terminal, and the nonvolatile memory circuit has a nonvolatile memory function and an input terminal of the nonvolatile memory circuit is connected to the output of the state detection enhancement circuit.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: April 17, 2012
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Mitsue Takahashi, Shigeki Sakai
  • Publication number: 20120085918
    Abstract: To improve an efficiency of utilizing electrons and efficiently suppress an ion beam spread by a space charge effect while eliminating a need for a special magnetic pole structure by effectively using a space in the vicinity of a magnet, there are provided an ion source, a collimating magnet and a plurality of electron sources, wherein the electron sources are arranged in a magnetic field gradient region formed on an ion beam upstream side or ion beam downstream side of the collimating magnet and arranged outside a region passed by the ion beam, and an irradiation direction of the electrons is directed to supply the electrons to the magnetic field gradient region.
    Type: Application
    Filed: April 27, 2010
    Publication date: April 12, 2012
    Applicants: KYOTO UNIVERSITY, NISSIN ION EQUIPMENT CO., LTD.
    Inventors: Dan Nicolaescu, Shigeki Sakai, Junzo Ishikawa, Yasuhito Gotoh
  • Patent number: 8139388
    Abstract: This invention has the purpose of providing a nonvolatile semiconductor storage device which is capable of entering multivalued storage in a FeFET unit without requiring preparation of a plurality of voltage sources. The nonvolatile semiconductor storage device is provided with multivalued ferroelectric memory cells which impart varied quantities of polarization to a ferroelectric material by applying pulse voltages having one and the same height and varied widths and consequently produce varied states of storage in conformity with the varied quantities of polarization.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: March 20, 2012
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Mitsue Takahashi, Shigeki Sakai, Shouyu Wang, Ken Takeuchi
  • Patent number: 8081499
    Abstract: A field-effect transistor for nonvolatile memory holding use and a field-effect transistor for logical operation use are manufactured in the same structure on the same semiconductor substrate without separately providing manufacturing processes for the field-effect transistors for the two uses. Both a memory circuit and a logic circuit of a semiconductor integrated circuit are composed of n-channel and p-channel field-effect transistors including a memory holding material in a gate insulating structure. A logical operation state, a memory writing state and a nonvolatile memory holding state are electrically switched by controlling the level and application timing of a voltage to be applied between a gate conductor and a substrate region of the n-channel and p-channel field-effect transistors including the memory holding material in the gate insulating structure.
    Type: Grant
    Filed: April 13, 2006
    Date of Patent: December 20, 2011
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Mitsue Takahashi, Shigeki Sakai
  • Patent number: 7935944
    Abstract: An ion beam irradiating apparatus has a field emission electron source 10 which is disposed in a vicinity of a path of the ion beam 2, and which emits electrons 12. The field emission electron source 10 is placed in a direction along which an incident angle formed by the electrons 12 emitted from the electron source 10 and a direction parallel to the traveling direction of the ion beam 2 is in the range from ?15 deg. to +45 deg. (an inward direction of the ion beam 2 is +, and an outward direction is ?).
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: May 3, 2011
    Assignees: Kyoto University, Nissin Ion Equipment Co., Ltd.
    Inventors: Junzo Ishikawa, Dan Nicolaescu, Yasuhito Gotoh, Shigeki Sakai
  • Publication number: 20110038201
    Abstract: There is provided a semiconductor integrated circuit including a state detection enhancement circuit which includes an input terminal and an output terminal and has a function of generating an electric potential of a magnitude capable of performing nonvolatile memory writing into a nonvolatile memory circuit based on an electric potential input to the input terminal and outputting the electric potential of the magnitude to the output terminal, and the nonvolatile memory circuit has a nonvolatile memory function and an input terminal of the nonvolatile memory circuit is connected to the output of the state detection enhancement circuit.
    Type: Application
    Filed: October 29, 2007
    Publication date: February 17, 2011
    Applicant: NATIONAL INSTITUTE OF ADVANCED IND.SCI AND TECH
    Inventors: Mitsue Takahashi, Shigeki Sakai
  • Publication number: 20100073988
    Abstract: This invention has the purpose of providing a nonvolatile semiconductor storage device which is capable of entering multivalued storage in a FeFET unit without requiring preparation of a plurality of voltage sources. The nonvolatile semiconductor storage device is provided with multivalued ferroelectric memory cells which impart varied quantities of polarization to a ferroelectric material by applying pulse voltages having one and the same height and varied widths and consequently produce varied states of storage in conformity with the varied quantities of polarization.
    Type: Application
    Filed: September 23, 2009
    Publication date: March 25, 2010
    Applicant: Nat Inst of Adv Industrial Sci and Tech
    Inventors: Mitsue TAKAHASHI, Shigeki Sakai, Shouyu Wang, Ken Takeuchi
  • Publication number: 20100057839
    Abstract: In a design-system distributing method, when a server side design system is updated, a server compares an updated server side design system and a client update state data, and the server distributes an update assisting system, an update indication data and a difference data to a client system based on the comparing result. The client system stores the update assisting system, the update indication data and the difference data, and the client system starts the stored update assisting system such that an update notice is outputted to a user of the client system to urge update of the client side design system each time a preset condition is satisfied until an update command of the client side design system is supplied to the client system. The client system updates the client side design system based on the stored update indication data and the stored difference data in response to the update command.
    Type: Application
    Filed: January 6, 2009
    Publication date: March 4, 2010
    Applicant: NEC Electronics Corporation
    Inventors: Shigeki Sakai, Kazuhiro Ando
  • Patent number: 7667252
    Abstract: To provide a semiconductor nonvolatile storage device capable of applying distributed voltage efficiently to a ferroelectric capacitor in a semiconductor nonvolatile storage device having an MFMIS structure without enlarging a memory cell area and a method of fabricating the same, a ferroelectric nonvolatile storage element is constructed by a structure successively laminated with a first insulator layer (3), a first conductor layer (4), a ferroelectric layer (5) and a second conductor layer (6) on a channel region and is constructed by a structure having a third conductor (9) and a fourth conductor (10) respectively laminated on a source region and a drain region, in which the third conductor (9) and the fourth conductor (10) are opposed to each other via the first conductor layer (4) and a second insulator thin film (11).
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: February 23, 2010
    Assignees: National Institute of Advanced Industrial Science and Technology, SEIKO NPC Corporation
    Inventors: Shigeki Sakai, Kazuo Sakamaki
  • Patent number: 7608307
    Abstract: A method of forming film on a substrate, in which in a preliminary step information on film thickness deposited on a test substrate prepared for use in collecting information over a fixed irradiation time is obtained in advance while shining a laser beam on a target, there being a fixed positional relationship between spatial positions of the test substrate and an incidence point of the laser beam on the target, or while shining the laser beam on the target while rotating the test substrate. In a main step, a deposition time at each relative positional relationship is adjusted based on film-thickness distribution information obtained in the preliminary step while spatially moving or rotating the substrate or substrate holder about a specific central axis of rotation relative to the incidence point of the laser beam to the target, or while performing both the relative rotation and relative movement.
    Type: Grant
    Filed: November 7, 2003
    Date of Patent: October 27, 2009
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventor: Shigeki Sakai
  • Publication number: 20090203199
    Abstract: An ion beam irradiating apparatus has a field emission electron source 10 which is disposed in a vicinity of a path of the ion beam 2, and which emits electrons 12. The field emission electron source 10 is placed in a direction along which an incident angle formed by the electrons 12 emitted from the electron source 10 and a direction parallel to the traveling direction of the ion beam 2 is in the range from ?15 deg. to +45 deg. (an inward direction of the ion beam 2 is +, and an outward direction is ?).
    Type: Application
    Filed: June 12, 2007
    Publication date: August 13, 2009
    Applicants: KYOTO UNIVERSITY, NISSIN ION EQUIPMENT CO., LTD.
    Inventors: Junzo Ishikawa, Dan Nicolaescu, Yasuhito Gotoh, Shigeki Sakai
  • Publication number: 20090059646
    Abstract: A field-effect transistor for nonvolatile memory holding use and a field-effect transistor for logical operation use are manufactured in the same structure on the same semiconductor substrate without separately providing manufacturing processes for the field-effect transistors for the two uses. Both a memory circuit and a logic circuit of a semiconductor integrated circuit are composed of n-channel and p-channel field-effect transistors including a memory holding material in a gate insulating structure. A logical operation state, a memory writing state and a nonvolatile memory holding state are electrically switched by controlling the level and application timing of a voltage to be applied between a gate conductor and a substrate region of the n-channel and p-channel field-effect transistors including the memory holding material in the gate insulating structure.
    Type: Application
    Filed: April 13, 2006
    Publication date: March 5, 2009
    Applicant: NATIONAL INSTITUTE OF ADVANCED IND. SCI & TECH
    Inventors: Mitsue Takahashi, Shigeki Sakai
  • Patent number: 7455030
    Abstract: A plasma generating apparatus is provided with a plasma generating apparatus for ionizing gas by high frequency discharge within a plasma generating container to thereby generate a plasma and for discharging the plasma to the outside through a plasma discharge hole, an antenna disposed within the plasma generating container for radiating a high frequency wave, an antenna cover made of an insulator and covering a whole of the antenna, a DC voltage measuring device for measuring a DC voltage between the antenna and the plasma generating container, and a comparator for comparing the DC voltage with a reference value, and outputting an alarm signal when an absolute value of the DC voltage value is larger than the absolute value of the reference value.
    Type: Grant
    Filed: March 6, 2008
    Date of Patent: November 25, 2008
    Assignee: Nissin Ion Equipment Co., Ltd.
    Inventor: Shigeki Sakai
  • Publication number: 20080218086
    Abstract: A plasma generating apparatus is provided with a plasma generating apparatus for ionizing gas by high frequency discharge within a plasma generating container to thereby generate a plasma and for discharging the plasma to the outside through a plasma discharge hole, an antenna disposed within the plasma generating container for radiating a high frequency wave, an antenna cover made of an insulator and covering a whole of the antenna, a DC voltage measuring device for measuring a DC voltage between the antenna and the plasma generating container, and a comparator for comparing the DC voltage with a reference value, and outputting an alarm signal when an absolute value of the DC voltage value is larger than the absolute value of the reference value.
    Type: Application
    Filed: March 6, 2008
    Publication date: September 11, 2008
    Applicant: NISSIN ION EQUIPMENT CO., LTD.
    Inventor: Shigeki Sakai
  • Publication number: 20080001194
    Abstract: To provide a semiconductor nonvolatile storage device capable of applying distributed voltage efficiently to a ferroelectric capacitor in a semiconductor nonvolatile storage device having an MFMIS structure without enlarging a memory cell area and a method of fabricating the same, a ferroelectric nonvolatile storage element is constructed by a structure successively laminated with a first insulator layer (3), a first conductor layer (4), a ferroelectric layer (5) and a second conductor layer (6) on a channel region and is constructed by a structure having a third conductor (9) and a fourth conductor (10) respectively laminated on a source region and a drain region, in which the third conductor (9) and the fourth conductor (10) are opposed to each other via the first conductor layer (4) and a second insulator thin film (11).
    Type: Application
    Filed: December 5, 2006
    Publication date: January 3, 2008
    Applicants: National Institute of Advanced Industrial Science and Technology, Nippon Precision Circuits Inc.
    Inventors: Shigeki Sakai, Kazuo Sakamaki
  • Patent number: 7226795
    Abstract: The MFIS transistors heretofore have a problem that after data writing, the data disappear in terms of memory transistor operation in about one day at most. This is mainly because the buffer layer and the ferroelectric have a high leakage current and, hence, charge is accumulated around the interface between the ferroelectric and the buffer layer so as to shield the electric polarization memorized by the ferroelectric, making it impossible for the electric polarization of the ferroelectric to control electrical conduction between the source and the drain in the transistor. In the present invention, by constituting an insulator buffer layer 2 of HfO2+u or Hf1?xAl2xO2+x+y, the leakage current flowing through each of the insulator buffer layer 2 and a ferroelectric 3 can be reduced and a memory transistor having a truly sufficient long data holding time is realized.
    Type: Grant
    Filed: August 19, 2003
    Date of Patent: June 5, 2007
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventor: Shigeki Sakai
  • Publication number: 20060246211
    Abstract: A method of forming film on a substrate, in which in a preliminary step information on film thickness deposited on a test substrate prepared for use in collecting information over a fixed irradiation time is obtained in advance while shining a laser beam on a target, there being a fixed positional relationship between spatial positions of the test substrate and an incidence point of the laser beam on the target, or while shining the laser beam on the target while rotating the test substrate. In a main step, a deposition time at each relative positional relationship is adjusted based on film-thickness distribution information obtained in the preliminary step while spatially moving or rotating the substrate or substrate holder about a specific central axis of rotation relative to the incidence point of the laser beam to the target, or while performing both the relative rotation and relative movement.
    Type: Application
    Filed: November 7, 2003
    Publication date: November 2, 2006
    Applicant: National Institute of Adv. Industrial Science and Tech.
    Inventor: Shigeki Sakai