Abstract: The MFIS transistors heretofore have a problem that after data writing, the data disappear in terms of memory transistor operation in about one day at most. This is mainly because the buffer layer and the ferroelectric have a high leakage current and, hence, charge is accumulated around the interface between the ferroelectric and the buffer layer so as to shield the electric polarization memorized by the ferroelectric, making it impossible for the electric polarization of the ferroelectric to control electrical conduction between the source and the drain in the transistor. In the present invention, by constituting an insulator buffer layer 2 of HfO2+u or Hf1?xAl2xO2+x+y, the leakage current flowing through each of the insulator buffer layer 2 and a ferroelectric 3 can be reduced and a memory transistor having a truly sufficient long data holding time is realized.

Abstract: A ferroelectric non-volatile memory device that allows the coupling ratio to be increased and the effect of voltage distribution to the ferroelectric capacitor to be improved without increasing the area of the gate electrode of a detection MIS field effect transistor is provided. In a memory cell structure, a semiconductor including regions for a source, a channel, and a drain, a gate insulator on the channel region, a floating gate conductor, a ferroelectrics, and an upper electrode conductor are layered in this order. The structure includes a paraelectric capacitor having one end connected to the floating gate conductor and the other end connected to the source region.

Abstract: To provide a semiconductor nonvolatile storage device capable of applying distributed voltage efficiently to a ferroelectric capacitor in a semiconductor nonvolatile storage device having an MFMIS structure without enlarging a memory cell area and a method of fabricating the same, a ferroelectric nonvolatile storage element is constructed by a structure successively laminated with a first insulator layer (3), a first conductor layer (4), a ferroelectric layer (5) and a second conductor layer (6) on a channel region and is constructed by a structure having a third conductor (9) and a fourth conductor (10) respectively laminated on a source region and a drain region, in which the third conductor (9) and the fourth conductor (10) are opposed to each other via the first conductor layer (4) and a second insulator thin film (11).

Abstract: To provide a semiconductor nonvolatile storage device capable of applying distributed voltage efficiently to a ferroelectric capacitor in a semiconductor nonvolatile storage device having an MFMIS structure without enlarging a memory cell area and a method of fabricating the same, a ferroelectric nonvolatile storage element is constructed by a structure successively laminated with a first insulator layer (3), a first conductor layer (4), a ferroelectric layer (5) and a second conductor layer (6) on a channel region and is constructed by a structure having a third conductor (9) and a fourth conductor (10) respectively laminated on a source region and a drain region, in which the third conductor (9) and the fourth conductor (10) are opposed to each other via the first conductor layer (4) and a second insulator thin film (11).

Abstract: The master slice type semiconductor integrated circuit includes sequential circuit cells (2) and combinational circuit cells (3), which are alternately arranged in an inner core area on a semiconductor chip (1), and a plurality of selective driving elements (MC101 to MC108, MC201 to MC216 and MC301 to MC316), which are connected in a shape of a tree, for selectively distributing a poliphase clock signal for each division area formed by uniformly dividing the inner core area. The plurality of selective driving elements are placed and connected on the semiconductor chip such that load and wiring length between the sequential circuit cells within the respective division areas and input terminals to which the poliphase clock signal is inputted are equal.

Abstract: An ion beam irradiation apparatus is provided with a plasma production device 30 which produces a plasma 12 through the radio frequency discharge and supplies the produced plasma in the vicinity of the substrate 4. The plasma production device 30 includes a plasma producing chamber 32 being elongated along an axis 33 extending in scanning directions X in which the ion beam is moved; a plasma emission hole 34 being provided in a side thereof and elongated along the axis 33 of the plasma producing chamber; and a magnet 36 provided outside the plasma producing chamber 32 for producing a magnetic field having a direction along the axis 33. The magnetic field developed by the magnet 36 contains a magnetic field which has a direction along the axis and bends to the substrate ions contained in the plasma 12 emitted from a plasma emission hole 34.

Abstract: A ferroelectric non-volatile memory device that allows the coupling ratio to be increased and the effect of voltage distribution to the ferroelectric capacitor to be improved without increasing the area of the gate electrode of a detection MIS field effect transistor is provided. In a memory cell structure, a semiconductor including regions for a source, a channel, and a drain, a gate insulator on the channel region, a floating gate conductor, a ferroelectrics, and an upper electrode conductor are layered in this order. The structure includes a paraelectric capacitor having one end connected to the floating gate conductor and the other end connected to the source region.

Abstract: When ion beam 14 is irradiated onto a substrate 2 to conduct processing such as ion injection, plasma 30 emitted from a plasma generating device 20 is supplied to a portion close to the substrate 2 to suppress electric charging on a substrate surface caused by ion beam irradiation. A ratio of IE/IB is kept at a value not lower than 1.8, a ratio of II /IE is kept at a value not lower than 0.07 and not higher than 0.7, wherein IB is an electric current of the ion beam 14 irradiated onto the substrate 2, II is an ion current expressing a quantity of ions in the plasma 30 emitted from the plasma generating device 20, and IE is an electron current expressing a quantity of electrons in the plasma 30.

Abstract: Terminal tools 16 are fixed to end portions of a plurality of wires 12 that are covered with a shield lacing 10, and a shield case 30 is connected/fixed to the shield lacing 10. End portions of respective wires 12 are inserted into a unit housing 40 of the electronic unit from the outside and connected to circuits in the unit housing 40, and then connected portions between respective wires 12 and a unit housing 40 are covered with the shield case 30 from the outside by fixing the shield case 30 to an outer surface of the unit housing 40. Also, the shield case 30 and the shield lacing 10 are brought into the state that they can be grounded via the unit housing 40.

Abstract: Terminal tools 16 are fixed to end portions of a plurality of wires 12 that are covered with a shield lacing 10, and a shield case 30 is connected/fixed to the shield lacing 10. End portions of respective wires 12 are inserted into a unit housing 40 of the electronic unit from the outside and connected to circuits in the unit housing 40, and then connected portions between respective wires 12 and a unit housing 40 are covered with the shield case 30 from the outside by fixing the shield case 30 to an outer surface of the unit housing 40. Also, the shield case 30 and the shield lacing 10 are brought into the state that they can be grounded via the unit housing 40.

Abstract: To provide a semiconductor nonvolatile storage device capable of applying distributed voltage efficiently to a ferroelectric capacitor in a semiconductor nonvolatile storage device having an MFMIS structure without enlarging a memory cell area and a method of fabricating the same, a ferroelectric nonvolatile storage element is constructed by a structure successively laminated with a first insulator layer (3), a first conductor layer (4), a ferroelectric layer (5) and a second conductor layer (6) on a channel region and is constructed by a structure having a third conductor (9) and a fourth conductor (10) respectively laminated on a source region and a drain region, in which the third conductor (9) and the fourth conductor (10) are opposed to each other via the first conductor layer (4) and a second insulator thin film (11).

Abstract: Disclosed is a connector having a terminal which is rendered into an electrically connectable state with a counterpart terminal by engaging with the counterpart terminal; a housing for accommodating the terminal therein; and an arc suppressive member which is provided at such a position as to be electrically connectable to the terminal and rendered into contact with the counterpart terminal when the terminal is being disengaged from the counterpart terminal so as to keep on electrically connecting the terminal and the counterpart terminal. The arc suppressive member has such a construction that an amount of discharged arc when the arc suppressive member is detached from the counterpart terminal is smaller than an amount of discharged arc when the terminal is disengaged from the counterpart terminal. With this arrangement, arc discharge at the disengagement of the terminals is suppressed.

Abstract: The master slice type semiconductor integrated circuit includes sequential circuit cells (2) and combinational circuit cells (3), which are alternately arranged in an inner core area on a semiconductor chip (1), and a plurality of selective driving elements (MC101 to MC108, MC201 to MC216 and MC301 to MC316), which are connected in a shape of a tree, for selectively distributing a poliphase clock signal for each division area formed by uniformly dividing the inner core area. The plurality of selective driving elements are placed and connected on the semiconductor chip such that load and wiring length between the sequential circuit cells within the respective division areas and input terminals to which the poliphase clock signal is inputted are equal.

Abstract: A charge-up measuring apparatus has a plurality of measurement conductors being arranged on a plane crossing an ion beam for receiving the ion beam, a plurality of bidirectional constant-voltage elements connected to the measurement conductors in a one-to-one correspondence, and a plurality of current measuring instruments each for measuring the polarity and the magnitude of an electric current flowing through the corresponding bidirectional constant-voltage element.

Abstract: An epitaxial compound structure has a crystal structure including fluorite crystal on which is epitaxially grown a film of simple perovskite crystal with a (011) orientation.

Abstract: Using an oxide superconductor that does not require cryogenic temperatures, a superconducting tunnel junction device is provided which can accurately control the magnitudes of critical current and step voltage necessary for electronics applications and which has good characteristics as designed. The intrinsic Josephson superconducting tunnel junction device includes an oxide superconductor defined by a general expression (I): Bi2−zPbzSr2Can(1−x)RnxCun+1O2n+6 (n≧1, 0<x≦0.2, 0≦z≦1.0, R: rare-earth element).

Abstract: Disclosed is a connector having a terminal which is rendered into an electrically connectable state with a counterpart terminal by engaging with the counterpart terminal; a housing for accommodating the terminal therein; and an arc suppressive member which is provided at such a position as to be electrically connectable to the terminal and rendered into contact with the counterpart terminal when the terminal is being disengaged from the counterpart terminal so as to keep on electrically connecting the terminal and the counterpart terminal. The arc suppressive member has such a construction that an amount of discharged arc when the arc suppressive member is detached from the counterpart terminal is smaller than an amount of discharged arc when the terminal is disengaged from the counterpart terminal. With this arrangement, arc discharge at the disengagement of the terminals is suppressed.

Abstract: An ion beam irradiation apparatus is provided with a plasma production device 30 which produces a plasma 12 through the radio frequency discharge and supplies the produced plasma in the vicinity of the substrate 4. The plasma production device 30 includes a plasma producing chamber 32 being elongated along an axis 33 extending in scanning directions X in which the ion beam is moved; a plasma emission hole 34 being provided in a side thereof and elongated along the axis 33 of the plasma producing chamber; and a magnet 36 provided outside the plasma producing chamber 32 for producing a magnetic field having a direction along the axis 33. The magnetic field developed by the magnet 36 contains a magnetic field which has a direction along the axis and bends to the substrate ions contained in the plasma 12 emitted from a plasma emission hole 34.

Abstract: When ion beam 14 is irradiated onto a substrate 2 to conduct processing such as ion injection, plasma 30 emitted from a plasma generating device 20 is supplied to a portion close to the substrate 2 to suppress electric charging on a substrate surface caused by ion beam irradiation. A ratio of IE/IB is kept at a value not lower than 1.8, a ratio of II /IE is kept at a value not lower than 0.07 and not higher than 0.7, wherein IB is an electric current of the ion beam 14 irradiated onto the substrate 2, II is an ion current expressing a quantity of ions in the plasma 30 emitted from the plasma generating device 20, and IE is an electron current expressing a quantity of electrons in the plasma 30.

Abstract: Terminal tools 16 are fixed to end portions of a plurality of wires 12 that are covered with a shield lacing 10, and a shield case 30 is connected/fixed to the shield lacing 10. End portions of respective wires 12 are inserted into a unit housing 40 of the electronic unit from the outside and connected to circuits in the unit housing 40, and then connected portions between respective wires 12 and a unit housing 40 are covered with the shield case 30 from the outside by fixing the shield case 30 to an outer surface of the unit housing 40. Also, the shield case 30 and the shield lacing 10 are brought into the state that they can be grounded via the unit housing 40.