Abstract: A semiconductor wafer and its manufacturing method are provided where the current driving capability of a MOS transistor can be sufficiently enhanced. An SOI layer wafer in which an SOI layer (32) is formed has a <100> crystal direction notch (32a) and a <110> crystal direction notch (32b). The SOI layer wafer and a supporting substrate wafer (1) are bonded to each other in such a way that the notch (32a) and a <110> crystal direction notch (1a) of the supporting substrate wafer (1) coincide with each other. When bonding the two wafers by using the notch (32a) and the notch (1a) to position the two wafers, the other notch (32b) of the SOI layer wafer can be engaged with a guide member of the semiconductor wafer manufacturing apparatus to prevent positioning error due to relative turn between the wafers.

Abstract: Provided is an MOS transistor capable of reducing gate overlap capacitance without decreasing the driving current of the MOS transistor. Specifically, a double-angle smile oxidation structure is obtainable by curving the side surface of a gate electrode (22) so as to widen upwardly, and thickening the edge portion of a gate oxide film (21) by re-oxidation. The impurity concentration of a source/drain layer under the double-angle smile oxidation structure (a region around point B) is set to the range of 4×1018 cm−3±40%.

Abstract: A channel region (2), a source region (3) and a drain region (4) are formed on a polycrystalline semiconductor layer (1). The characteristic of a polycrystalline TFT (101) is dispersed by the amount of crystal grain boundaries (6) contained in the channel region (2). A drain current is reduced as the amount of the crystal grain boundaries (6) contained in the channel region (2) is increased. In order to utilize a code obtained by encoding the electric characteristic of the TFT (101) for identification of a semiconductor chip, a system or the like, the TFT (101) is mounted on the semiconductor chip, the system or the like along with an encoder circuit. Thus, a barrier against illegal use of a user terminal is improved at a low cost.

Abstract: A code generation unit (400) generates an identification code (Cd) inherent in a semiconductor substrate (CH1 or CH3). A memory (601) formed in another semiconductor substrate (CH2) stores the identification code (Cd) as a memory code (Co). The identification code (Cd) is written from the code generation unit (400) to the memory (601) before shipment of a semiconductor device (600) as a product. A comparator circuit (403) compares the identification code (Cd) with the memory code (Co) and stops some of operations of a predetermined circuit (405) when the two codes do not coincide with each other. With this construction, a higher technical barrier (security) against fraudulent use of an appliance of the semiconductor device through replacement of the semiconductor substrate can be achieved.

Abstract: A memory cell includes an n well and a p well. A word line is provided over memory cell and n well and p well are arranged in a direction in which word line extends. A single word line is provided for each memory cell and formed of metal.

Abstract: In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.

Abstract: A plurality of word lines (WL1) are provided in parallel to one another and a plurality of bit lines (BL1) are provided in parallel to one another, intersecting the word lines (WL1) thereabove. MRAM cells (MC2) are formed at intersections of the word lines and the bit lines therebetween. MRAM cells (MC3) are provided so that an easy axis indicated by the arrow has an angle of 45 degrees with respect to the bit lines and the word lines. Thus, an MRAM capable of cutting the power consumption in writing is achieved and further an MRAM capable of reducing the time required for erasing and writing operations is achieved.

Abstract: It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film (11) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gate electrode (12) and an SOI layer (3), and a gate insulating film (110) having a thickness of 5 to 15 nm is provided between the gate contact pad (GP) and the SOI layer (3). The gate insulating film (11) and the gate insulating film (110) are provided continuously.

Abstract: A code generation unit generates an identification code inherent in a semiconductor substrate. A memory formed in another semiconductor substrate stores the identification code as a memory code. The identification code is written from the code generation unit to the memory before shipment of a semiconductor device as a product. A comparator circuit compares the identification code with the memory code and stops some operations of a predetermined circuit when the two codes do not coincide with each other. With this construction, a higher technical barrier (security) against fraudulent use of an appliance of the semiconductor device through replacement of the semiconductor substrate can be achieved.

Abstract: A channel region (2), a source region (3) and a drain region (4) are formed on a polycrystalline semiconductor layer (1). The characteristic of a polycrystalline TFT (101) is dispersed by the amount of crystal grain boundaries (6) contained in the channel region (2). A drain current is reduced as the amount of the crystal grain boundaries (6) contained in the channel region (2) is increased. In order to utilize a code obtained by encoding the electric characteristic of the TFT (101) for identification of a semiconductor chip, a system or the like, the TFT (101) is mounted on the semiconductor chip, the system or the like along with an encoder circuit. Thus, a barrier against illegal use of a user terminal is improved at a low cost.

Abstract: A semiconductor device having an inductor is provided. In an RF circuit portion (RP), a region in an SOI layer (3) corresponding to a region in which a spiral inductor (SI) is provided is divided into a plurality of SOI regions (21) by a plurality of trench isolation oxide films (11). The trench isolation oxide films (11) are formed by filling trenches extending from the surface of the SOI layer (3) to the surface of a buried oxide film (2) with a silicon oxide film, and completely electrically isolate the SOI regions (21) from each other. The trench isolation oxide films (11) have a predetermined width and are shaped to extend substantially perpendicularly to the surface of the buried oxide film (2). The semiconductor device is capable of reducing electrostatically induced power dissipation and electromagnetically induced power dissipation, and preventing the structure and manufacturing steps thereof from becoming complicated.

Abstract: The invention relates to improvements in a method of manufacturing a semiconductor device in which deterioration in a transistor characteristic is avoided by preventing a channel stop implantation layer from being formed in an active region. After patterning a nitride film (22), the thickness of an SOI layer 3 is measured (S2) and, by using the result of measurement, etching conditions (etching time and the like) for SOI layer 3 are determined (S3). To measure the thickness of SOI layer 3, it is sufficient to use spectroscopic ellipsometry which irradiates the surface of a substance with linearly polarized light and observes elliptically polarized light reflected by the surface of a substance. The etching condition determined is used and a trench TR2 is formed by using patterned nitride film 22 as an etching mask (S4).

Abstract: The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask (RM12) is formed so as to have an opening over a region (PR) in which a PMOS transistor is formed. Channel stop implantation is performed with energy by which ions pass through a partial isolation oxide film (PT11) and a peak of an impurity profile is generated in an SOI layer (3), thereby forming a channel stop layer (N1) in the SOI layer (3) under the partial isolation oxide film (PT11), that is, an isolation region. An impurity to be implanted here is an N-type impurity. In the case of using phosphorus, its implantation energy is set to, for example, 60 to 120 keV, and the density of the channel stop layer (N1) is set to 1×1017 to 1x1019/cm3.

Abstract: In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.

Abstract: A semiconductor device with a spiral inductor is provided, which determines the area of an insulation layer to be provided in the surface of a wiring board thereunder. A trench isolation oxide film (19), which is a complete isolation oxide film including in part the structure of a partial isolation oxide film, is provided in a larger area of the surface of an SOI layer (3) than that corresponding to the area of a spiral inductor (SI). The trench isolation oxide film (19) is comprised of a first portion (191) having a first width and extending in a direction approximately perpendicular the surface of a buried oxide film (2), and a second portion (192) having a second width smaller than the first width and being continuously formed under the first portion (191), extending approximately perpendicular to the surface of the buried oxide film (2).

Abstract: Obtained is a method of manufacturing a semiconductor device which can take a body contact while electrically isolating an NMOS transistor and a PMOS transistor from each other through a complete isolation. First of all, element isolating films (7a to 7c) of a partial isolation type are formed in a first main surface of a silicon layer (3). Next, a PMOS transistor, an NMOS transistor, a multilayer wiring structure, a spiral inductor (20) and a pad (22) are formed, respectively. Then, a support substrate (23) is formed over the whole surface. Thereafter, a silicon substrate (1) and a BOX layer (2) are removed to expose a second main surface of the silicon layer (3). Subsequently, element isolating films (27a to 27d) connected to the element isolating films (7a and 7b) are formed on the second main surface side of the silicon layer (3). Consequently, a complete isolation can be obtained.

Abstract: Provided are a semiconductor device that optimizes the operation characteristics such as of both an insulating gate type transistor for high voltage and an insulating gate type transistor for low voltage, and a method of manufacturing the same. Specifically, a patterned resist (25) is formed so as to cover a low voltage operation region (A2), a second LDD implantation process of implanting an impurity ion (14) by using the resist (25) as a mask, is performed over a silicon oxide film (6) thereby to form an impurity diffusion region (13) in the surface of a semiconductor substrate (1) in a high voltage operation region (A1). After this step, the silicon oxide film (6) in the high voltage operation region (A1) contains the impurity during the second LDD implantation process whereas the silicon oxide film (6) in a low voltage operation region (A2) contains no impurity.

Abstract: A plurality of word lines (WL1) are provided in parallel to one another and a plurality of bit lines (BL1) are provided in parallel to one another, intersecting the word lines (WL1) thereabove. MRAM cells (MC2) are formed at intersections of the word lines and the bit lines therebetween. MRAM cells (MC3) are provided so that an easy axis indicated by the arrow has an angle of 45 degrees with respect to the bit lines and the word lines. Thus, an MRAM capable of cutting the power consumption in writing is achieved and further an MRAM capable of reducing the time required for erasing and writing operations is achieved.

Abstract: As a first semiconductor element and a second semiconductor element, provided are two p-type MOS transistors for forming an element pair. These MOS transistors are compared with each other in electronic characteristic and a result of which is utilized for determining binary logic for the element pair. These MOS transistors are integrated and hence, they are equally subjected to ambient temperature. As a result, the result of comparison therebetween in electronic characteristic is unlikely to be subjected to ambient temperature.

Abstract: As a first semiconductor element and a second semiconductor element, provided are two p-type MOS transistors (11a, 11b) for forming an element pair (11). These MOS transistors (11a, 11b) are compared with each other in electronic characteristic and a result of which is utilized for determining binary logic for the element pair (11). These MOS transistors (11a, 11b) are integrated and hence, they are equally subjected to ambient temperature. As a result, the result of comparison therebetween in electronic characteristic is unlikely to be subjected to ambient temperature.