Abstract: Obtained is a method of manufacturing a semiconductor device which can take a body contact while electrically isolating an NMOS transistor and a PMOS transistor from each other through a complete isolation. First of all, element isolating films (7a to 7c) of a partial isolation type are formed in a first main surface of a silicon layer (3). Next, a PMOS transistor, an NMOS transistor, a multilayer wiring structure, a spiral inductor (20) and a pad (22) are formed, respectively. Then, a support substrate (23) is formed over the whole surface. Thereafter, a silicon substrate (1) and a BOX layer (2) are removed to expose a second main surface of the silicon layer (3). Subsequently, element isolating films (27a to 27d) connected to the element isolating films (7a and 7b) are formed on the second main surface side of the silicon layer (3). Consequently, a complete isolation can be obtained.

Abstract: A memory cell includes an n well and a p well. A word line is provided over memory cell and n well and p well are arranged in a direction in which word line extends. A single word line is provided for each memory cell and formed of metal.

Abstract: A first impurity diffusion layer forms one of source/drain regions and also forms a bit line. A first semiconductor layer, a channel semiconductor layer and a second semiconductor layer, which forms the other of source/drain regions and also forms a storage node, are disposed on the first impurity diffusion layer. A capacitor insulating film is disposed on a second conductive layer. A cell plate is disposed on a storage node with the capacitor insulating film therebetween. A capacitance of the bit line is reduced, and a dynamic random access memory thus constructed performs a high-speed operation.

Abstract: Provided are a semiconductor device that optimizes the operation characteristics such as of both an insulating gate type transistor for high voltage and an insulating gate type transistor for low voltage, and a method of manufacturing the same. Specifically, a patterned resist (25) is formed so as to cover a low voltage operation region (A2), a second LDD implantation process of implanting an impurity ion (14) by using the resist (25) as a mask, is performed over a silicon oxide film (6) thereby to form an impurity diffusion region (13) in the surface of a semiconductor substrate (1) in a high voltage operation region (A1). After this step, the silicon oxide film (6) in the high voltage operation region (A1) contains the impurity during the second LDD implantation process whereas the silicon oxide film (6) in a low voltage operation region (A2) contains no impurity.

Abstract: A memory cell which is capable of reducing the memory cell size in SRAM using a field-shield isolation on an SOI substrate. An isolation oxide film is provided between a field-shield isolation plate for n-type transistors and a field-shield isolation plate for p-type transistors.

Abstract: Obtained is a method of manufacturing a semiconductor device which can take a body contact while electrically isolating an NMOS transistor and a PMOS transistor from each other through a complete isolation. First of all, element isolating films (7a to 7c) of a partial isolation type are formed in a first main surface of a silicon layer (3). Next, a PMOS transistor, an NMOS transistor, a multilayer wiring structure, a spiral inductor (20) and a pad (22) are formed, respectively. Then, a support substrate (23) is formed over the whole surface. Thereafter, a silicon substrate (1) and a BOX layer (2) are removed to expose a second main surface of the silicon layer (3). Subsequently, element isolating films (27a to 27d) connected to the element isolating films (7a and 7b) are formed on the second main surface side of the silicon layer (3). Consequently, a complete isolation can be obtained.

Abstract: A semiconductor device comprises a silicon region (1) of the first conductivity type, a porous silicon layer (2) formed inside the silicon region (1) as a buried layer and a source region (3a) and a drain region (4a) of the second conductivity type different from the first conductivity type selectively formed in an upper surface of the silicon region (1). Bottom surfaces of the source region (3a) and the drain region (4a) are located adjacently above an upper surface of the porous silicon layer (2). As a result, depletion layers (8) in pn junctions between the silicon region (1) and the bottom surfaces of the source region (3a) and the drain region (4a) reach the inside of the porous silicon layer (2). With this structure, a semiconductor device which achieves a faster operation and lower power consumption while ensuring stability in operation of a MOSFET and a method of manufacturing the same are provided.

Abstract: A memory cell includes an n well and a p well. A word line is provided over memory cell and n well and p well are arranged in a direction in which word line extends. A single word line is provided for each memory cell and formed of metal.

Abstract: An object is to obtain a semiconductor in which the body potential can be externally fixed with a body potential fixing portion and in which no semiconductor region where ions of different conductivity types are mixed exists. A semiconductor layer (10) on an insulating layer (20) has an under semiconductor layer (10b) under an element isolation portion (14) and a body (10a) under a closed-loop portion (150). A gate structure (15) has gate pads (151) and the closed-loop portion (150). While a body potential fixing portion (13) is located on the opposite side of the element isolation portion (14) from the gate structure (15), the gate structure (15) is formed from the semiconductor layer (10) to extend on the element isolation portion (14). Accordingly, the body potential fixing portion (13) can be connected to the body (10a) through the under semiconductor layer (10b) without through the pn junction formed by the source (12) and the semiconductor layer (10).

Abstract: A code generation unit (400) generates an identification code (Cd) inherent in a semiconductor substrate (CH1 or CH3). A memory (601) formed in another semiconductor substrate (CH2) stores the identification code (Cd) as a memory code (Co). The identification code (Cd) is written from the code generation unit (400) to the memory (601) before shipment of a semiconductor device (600) as a product. A comparator circuit (403) compares the identification code (Cd) with the memory code (Co) and stops some of operations of a predetermined circuit (405) when the two codes do not coincide with each other. With this construction, a higher technical barrier (security) against fraudulent use of an appliance of the semiconductor device through replacement of the semiconductor substrate can be achieved.

Abstract: All source regions belonging to a row are electrically connected to one another through a silicon layer (4) in a portion between a bottom surface of a partial-isolation insulating film (5) and an upper surface of a BOX layer (3). These constitute source lines (SL1 to SL5) extending like strips in a row direction. The isolation insulating film (5) between the source regions adjacent to each other in the row direction is removed and in the silicon layer (4) of the portion exposed by removing the isolation insulating film (5), an impurity introduction region (10) having the same conductivity type as the source region has is formed. With this structure, a nonvolatile semiconductor memory device which causes no malfunction due to driving of a parasitic bipolar transistor can be provided.

Abstract: A semiconductor device and a manufacturing method thereof are obtained which can restrain increase of the parasitic capacitance generated between contact plugs of source/drain regions and a gate electrode while reducing the area of the source/drain regions. A channel region is formed under a gate electrode 1. A pair of source/drain regions 2 are formed to sandwich the channel region. The source/drain regions 2 have a first part 3a being adjacent to the channel region and a second part 3b formed to protrude in a channel width direction from the first part 3a so that a part of outer peripheries of the source/drain regions 2 extend away from the gate electrode 1 in a plan view. Contact plugs 4 are formed on the second part 3b for connecting the source/drain regions 2 to source/drain wirings.

Abstract: In a method of evaluating the reliability of a thin film transistor (TFT), time coefficient &bgr;, voltage coefficient d and temperature coefficient &phgr;0 are experimentally produced from −BT stress tests, and the life of a TFT under −BT stress conditions is evaluated using the following expression: τ = t 0 ⁡ ( Δ ⁢   ⁢ V th ⁢   ⁢ τ

Abstract: A memory cell includes an n well and a p well. A word line is provided over memory cell and n well and p well are arranged in a direction in which word line extends. A single word line is provided for each memory cell and formed of metal.

Abstract: A semiconductor device for CSP mounting which avoids errors due to alpha rays and is highly stress-resistant is provided. A buried oxide film (107) is formed on a semiconductor substrate (101), and a MOS transistor having an SOI structure is formed on the buried oxide film (107). The MOS transistor comprises source and drain regions (120a, 120b) formed in a semiconductor layer (120), and a gate electrode (110). An aluminum pad (103) connected to any one of the source and drain regions (120a, 120b) through a connecting mechanism not shown, and a silicon nitride film (104) having an opening on the top of the aluminum pad (103) are formed on an interlayer insulation film (108). A layer of titanium (105) and a layer of nickel (106) are formed extending from the aluminum pad (103) to an end of the silicon nitride film (104). A solder bump (11) is disposed on the layer of nickel (106).

Abstract: A semiconductor substrate and a method of fabricating a semiconductor device are provided. An oxide film (13) is formed by oxidizing an edge section and a lower major surface of an SOI substrate (10). This oxidizing step is performed in a manner similar to LOCOS (Local Oxide of Silicon) oxidation by using an oxide film (11) exposed on the edge section and lower major surface of the SOI substrate (10) as an underlying oxide film. Then, the thickness of the oxide film (13) is greater than that of the oxide film (11) on the edge section and lower major surface of the SOI substrate (10). The semiconductor substrate prevents particles of dust from being produced at the edge thereof.

Abstract: In a method of evaluating the reliability of a TFT, time coefficient &bgr;, voltage coefficient d and temperature coefficient &phgr;0 are experimentally produced from −BT stress tests, and the life of a TFT under −BT stress conditions is evaluated using the following expression: 1 τ = t 0 ⁡ ( Δ ⁢   ⁢ V th ⁢   ⁢ τ Δ ⁢   ⁢ V th0 ) β ⁢   ⁢ exp ⁢   ⁢ β ⁢   ⁢ q ⁢   ⁢ φ 0 kT ⁢ exp ⁢   ⁢ ( - β ⁢   ⁢ qd ⁢ &LeftBracketingBar; V G &RightBracketingBar; 2 ⁢ kTt OX ) ( 8 )

Abstract: An SOI layer is formed so thick that a body region is not fully depleted under conditions of floating and a zero potential. When a MOSFET operates, a negative body potential is applied to the body region through a body electrode. Thus, the body region is fully depleted. The MOSFET is formed equivalently to a conventional MOSFET of a PD mode as to the thickness of the SOI layer, and is equivalent to a MOSFET of an FD mode as to its operation. Therefore, both of advantages of a PD mode MOSFET such as low resistance in source/drain regions, easiness in formation of a contact hole for a main electrode and stability of a silicide layer and an advantage of an FD mode MOSFET such as excellent switching characteristics are compatibly implemented.

Abstract: An SOI layer is formed on a silicon substrate with a buried insulating layer therebetween. An SOI-MOSFET is formed including a drain region and a source region that are formed to define a channel formation region at the SOI layer and including a gate electrode layer opposite to the channel formation region with an insulating layer therebetween. An FS isolation structure is formed to have an FS plate opposite to a region of the SOI layer in the vicinity of the edge portion of the drain region and the source region, and to electrically isolate the SOI-MOSFET from other elements by applying a prescribed potential to the FS plate to fix the potential of the region of the SOI layer opposite to the FS plate. The channel formation region includes two edge portions on both sides and a central portion between the edge portions in a direction of a channel width, and a channel length at the edge of a prescribed region is smaller than a channel length at the central portion.

Abstract: A first impurity diffusion layer forms one of source/drain regions and also forms a bit line. A first semiconductor layer, a channel semiconductor layer and a second semiconductor layer, which forms the other of source/drain regions and also forms a storage node, are disposed on the first impurity diffusion layer. A capacitor insulating film is disposed on a second conductive layer. A cell plate is disposed on a storage node with the capacitor insulating film therebetween. A capacitance of the bit line is reduced, and a dynamic random access memory thus constructed performs a high-speed operation.