Abstract: A freezer (106) is provided with a connector (120) and connected to a semiconductor equipment (10). The connector (120) may include a connector for power supply (120a), a connector for data communication (120b) and a connector for analog signal (120c). Therefore, the semiconductor equipment (10) can transmit data and signal to the outside while being cooled in the freezer (106). With this constitution, a semiconductor equipment housed in a cooling system for high-speed operation and a refrigerator for cooling the semiconductor equipment are provided.

Abstract: A method of manufacturing a semiconductor memory device comprising: a step of forming a storage node in which a conductive layer 7 to be the storage node is formed in the vicinity of single crystalline silicon 3 formed on an insulator 2, a gettering step for conducting heat treatment to the single crystalline silicon 3 after the step of forming the storage node and gettering contaminants contained in the single crystalline silicon 3 by the conductive layer 7 connected to the single crystalline silicon, and a step of forming a gate oxide film 8a on the single crystalline silicon 3 after the step of gettering is provided to thereby obtain a sufficient gettering effect even though the width of an element and/or the thickness of the element is reduced in accordance with microminiaturization of the element.

Abstract: A semiconductor device with a spiral inductor is provided, which determines the area of an insulation layer to be provided in the surface of a wiring board thereunder. A trench isolation oxide film, which is a complete isolation oxide film including in part the structure of a partial isolation oxide film, is provided in a larger area of the surface of an SOI layer than that corresponding to the area of a spiral inductor. The trench isolation oxide film is comprised of a first portion having a first width and extending in a direction approximately perpendicular the surface of a buried oxide film, and a second portion having a second width smaller than the first width and being continuously formed under the first portion, extending approximately perpendicular to the surface of the buried oxide film.

Abstract: In a gate array, a gate length is measured by dividing gate electrodes into groups according to their materials to distinguish between those groups. The shape of a contact pad portion (5) of a gate electrode (4) differs according to the groups. A difference described here appears as shape such as cutouts (6a-6c) or projections (6d-6f), which is distinguishable by a scanning electron microscope, for example.

Abstract: It is an object to obtain a semiconductor device including a capacitance having a great Q-value. In an SOI substrate comprising a support substrate (165), a buried oxide film (166) and an SOI layer (171), an isolating oxide film 167 (167a to 167c) is selectively formed in an upper layer portion of the SOI layer (171) with a part of the SOI layer (171) remaining as a P− well region (169). Consequently, an isolation (partial isolation) structure is obtained. An N+ diffusion region (168) is formed in the SOI layer (171) between the isolating oxide films (167a) and (167b) and a P+ diffusion region (170) is formed in the SOI layer (171) between the isolating oxide films (167b) and (167c). Consequently, there is obtained a junction type variable capacitance (C23) having a PN junction surface of the P− well region (169) provided under the isolating oxide film (167b) and the N+ diffusion region (168).

Abstract: An SOI layer (4) is provided in a buried oxide film (2) and a source (51) and a drain (52) are provided on the upper surface of the SOI layer (4) so that they are kept from contact with the buried oxide film (2). A depletion layer (90) formed by the source (51), the drain (52), and the SOI layer (4) extends to reach the buried oxide film (2), so parasitic capacitance is reduced. This structure achieves an SOIMOS transistor capable of reducing junction capacitance at low drain voltage.

Abstract: It is an object to obtain a semiconductor device having such a structure that respective electrical characteristics of an insulated gate type transistor and an insulated gate type capacitance are not deteriorated and a method of manufacturing the semiconductor device. An NMOS transistor Q1 and a PMOS transistor Q2 which are formed in an NMOS formation region A1 and a PMOS formation region A2 respectively have P− pocket regions 17 and N− pocket regions 27 in vicinal regions of extension portions 14e and 24e of N+ source-drain regions 14 and P+ source-drain regions 24, respectively. On the other hand, an N-type variable capacitance C1 and a P-type variable capacitance C2 which are formed in an N-type variable capacitance formation region A3 and a P-type variable capacitance formation region A4 respectively do not have a region of a reverse conductivity type which is adjacent to extraction electrode regions corresponding to the P− pocket regions 17 and the N− pocket regions 27.

Abstract: A freezer (106) is provided with a connector (120) and connected to a semiconductor equipment (10). The connector (120) may include a connector for power supply (120a), a connector for data communication (120b) and a connector for analog signal (120c). Therefore, the semiconductor equipment (10) can transmit data and signal to the outside while being cooled in the freezer (106). With this constitution, a semiconductor equipment housed in a cooling system for high-speed operation and a refrigerator for cooling the semiconductor equipment are provided.

Abstract: A semiconductor device which achieves reductions in malfunctions and operating characteristic variations by reducing the gain of a parasitic bipolar transistor, and a method of manufacturing the same are provided. A silicon oxide film (6) is formed partially on the upper surface of a silicon layer (3). A gate electrode (7) of polysilicon is formed partially on the silicon oxide film (6). A portion of the silicon oxide film (6) underlying the gate electrode (7) functions as a gate insulation film. A silicon nitride film (9) is formed on each side surface of the gate electrode (7), with a silicon oxide film (8) therebetween. The silicon oxide film (8) and the silicon nitride film (9) are formed on the silicon oxide film (6). The width (W1) of the silicon oxide film (8) in a direction of the gate length is greater than the thickness (T1) of the silicon oxide film (6).

Abstract: Provided are a semiconductor device that optimizes the operation characteristics such as of both an insulating gate type transistor for high voltage and an insulating gate type transistor for low voltage, and a method of manufacturing the same. Specifically, a patterned resist (25) is formed so as to cover a low voltage operation region (A2), a second LDD implantation process of implanting an impurity ion (14) by using the resist (25) as a mask, is performed over a silicon oxide film (6) thereby to form an impurity diffusion region (13) in the surface of a semiconductor substrate (1) in a high voltage operation region (A1). After this step, the silicon oxide film (6) in the high voltage operation region (A1) contains the impurity during the second LDD implantation process whereas the silicon oxide film (6) in a low voltage operation region (A2) contains no impurity.

Abstract: A semiconductor device having an SOI structure capable of effectively preventing diffusion of an impurity from a source/drain region on an endmost portion of a silicon layer under a gate electrode is disclosed. In this semiconductor device, nitrogen is introduced into at least either a source/drain region or an end portion of a semiconductor layer located under a gate electrode, and the concentration profile of the nitrogen has a first concentration peak at least in either one of an endmost portion of the source/drain region in the direction where the gate electrode extends and an endmost portion of the semiconductor layer located under the gate electrode. Due to this concentration profile of nitrogen, point defects or the like serving as mediation for diffusion of an impurity are trapped, whereby diffusion of the impurity from the source/drain region is inhibited as a result. Thus, generation of an abnormal leakage current or the like is prevented.

Abstract: In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.

Abstract: It is an object to provide a music delivery system capable of delivering a music with which each listener can easily gain sympathy. There are provided a delivery server (1) for storing musical accompaniment data and lyrics data (voice data, that is, text data for a karaoke delivery system) of a plurality of tunes and for delivering the same data on request, and a receiving terminal (2) for giving a request for delivering data to the delivery server (1) and receiving the delivery upon receipt of an instruction from a user. In such a music delivery system, for example, a part of the lyrics data are constituted by a change data block which can be changed and are changed depending on a position of presence of the receiving terminal. For example, a tune of “Woman in Nagoya” is transmitted to a receiving terminal in Nagoya and the “Nagoya” in a title of the “Woman in Nagoya” and lyrics is changed into “Hakata” to be delivered to a receiving terminal in Hakata.

Abstract: An inductor recognition method for recognizing an inductor, a layout inspection method wherein it is possible to automatically carry out a verification of a design standard, in the inductor and a process for a semiconductor device using this layout inspection method are provided. The inductor recognition method includes the step of arranging an inductor position representation mark so as to surround a design pattern of an interconnection part, which works as an inductor and has a starting point and a finishing point; the step of arranging a starting point position representation mark and a finishing point position representation mark so as to surround, respectively, regions corresponding to the starting point and the finishing point; and the step of recognizing information with respect to an inductor by means of the inductor position representation mark, the starting point position representation mark and the finishing point position representation mark.

Abstract: A field effect transistor occupying a small area and a semiconductor device using the same can be obtained. A gate electrode is provided on a substrate on which a source region is provided with a first interlayer insulating film interposed therebetween. The gate electrode is covered with a second interlayer insulating film. A contact hole for exposing a part of the surface of the source region is provided so as to penetrate through the first interlayer insulating film, the gate electrode, and the second interlayer insulating film. A sidewall surface of the contact hole is covered with a gate insulating film. A first semiconductor layer of a first conductivity type is provided on the surface of the source region in contact therewith up to the lower surface of the gate electrode. A channel semiconductor layer is provided on the surface of the first semiconductor layer up to the upper surface of the gate electrode.

Abstract: A semiconductor device having an inductor is provided. In an RF circuit portion (RP), a region in an SOI layer (3) corresponding to a region in which a spiral inductor (SI) is provided is divided into a plurality of SOI regions (21) by a plurality of trench isolation oxide films (11). The trench isolation oxide films (11) are formed by filling trenches extending from the surface of the SOI layer (3) to the surface of a buried oxide film (2) with a silicon oxide film, and completely electrically isolate the SOI regions (21) from each other. The trench isolation oxide films (11) have a predetermined width and are shaped to extend substantially perpendicularly to the surface of the buried oxide film (2). The semiconductor device is capable of reducing electrostatically induced power dissipation and electromagnetically induced power dissipation, and preventing the structure and manufacturing steps thereof from becoming complicated.

Abstract: According to a semiconductor device and a method of manufacturing the same, a trade-off relationship between threshold values and a diffusion layer leak is eliminated and it is not necessary to form gate oxide films at more than one stages. Since impurity dose are different from each other between gate electrodes (4A to 4C) of N-channel type MOS transistors (T41 to T43), impurity concentration in the gate electrodes (4A to 4C) are different from each other. The impurity concentration in the gate electrodes are progressively lower in the order of higher threshold values which are expected.

Abstract: An SOI layer is provided in a buried oxide film and a source and a drain are provided on the upper surface of the SOI layer so that they are kept from contact with the buried oxide film. A depletion layer formed by the source, the drain, and the SOI layer extends to reach the buried oxide film, so parasitic capacitance is reduced. This structure achieves an SOIMOS transistor capable of reducing junction capacitance at low drain voltage.

Abstract: A method for collecting semiconductor devices and a method for selling and using semiconductor devices in consideration of collection are provided. When a user of an electrical appliance containing a semiconductor chip discards the electrical appliance, the user disassembles the electrical appliance and removes the semiconductor chip from the printed board on which it is mounted (S1). The user can thus obtain a service number provided on the back (S2) and in step S3 reports the service number to the manufacturer of the electrical appliance, or the manufacturer of the semiconductor chip, or a service organization acting for the purpose of collection. When receiving the report, the manufacturer or the service organization gives a reward to the user (S4) and separately collects the semiconductor chip (S5).

Abstract: A semiconductor device with a spiral inductor is provided, which determines the area of an insulation layer to be provided in the surface of a wiring board thereunder. A trench isolation oxide film (19), which is a complete isolation oxide film including in part the structure of a partial isolation oxide film, is provided in a larger area of the surface of an SOI layer (3) than that corresponding to the area of a spiral inductor (SI). The trench isolation oxide film (19) is comprised of a first portion (191) having a first width and extending in a direction approximately perpendicular the surface of a buried oxide film (2), and a second portion (192) having a second width smaller than the first width and being continuously formed under the first portion (191), extending approximately perpendicular to the surface of the buried oxide film (2).