Patents by Inventor Shigenori Hayashi

Shigenori Hayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190302513
    Abstract: A display device includes: a display panel including a substrate and a display driving component mounted on the substrate; a backlight unit; and a heat dissipation member present on that surface of the substrate which is opposite to the region in which a display driving component is mounted and on that side of the backlight unit which is opposite to the display panel, the heat dissipation member being made of a highly thermally conductive material and having slits for discharging gas inside the heat dissipation member to outside the heat dissipation member.
    Type: Application
    Filed: February 21, 2019
    Publication date: October 3, 2019
    Inventors: TOMOYA IDE, SHIGENORI MORIOKA, TOKUMI HAYASHI
  • Publication number: 20190302351
    Abstract: A display device includes a display panel and a backlight. The display panel includes a first substrate, a second substrate, and a heatsink. The first substrate includes a second substrate non-overlapping portion on which the second substrate is not disposed but a driving component is disposed. The backlight includes a light guide plate and a light source. The light source emits light toward an end surface of the light guide plate. The heatsink includes a display panel overlapping portion, a light source overlapping portion, and a connecting portion. The display panel overlapping portion is on a rear surface of the first substrate at least over an area corresponding to the driving component. The light source overlapping portion is on a side of the backlight remote from the display panel. The connecting portion connects the display panel overlapping portion and the light source overlapping portion to each other.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 3, 2019
    Inventors: TOKUMI HAYASHI, TOMOYA IDE, SHIGENORI MORIOKA
  • Publication number: 20190293439
    Abstract: A vehicle control device includes a terminal device authentication unit configured to determine whether a terminal device of a user registered as a user of a vehicle in advance is present around or within the vehicle, a communication unit configured to communicate with the terminal device, and a control unit configured to cause a display device provided in the vehicle to output a screen for setting communication between the communication unit and the terminal device in a case where it is determined by the terminal device authentication unit that the terminal device is present and the display device is started up.
    Type: Application
    Filed: March 15, 2019
    Publication date: September 26, 2019
    Inventors: Shigenori Hiruta, Takashi Mori, Hiroyuki Hayashi
  • Patent number: 10290803
    Abstract: A wedge-shaped contact region can be employed to provide electrical contacts to multiple electrically conductive layers in a three-dimensional device structure. A cavity including a generally wedge-shaped region and a primary region is formed in a dielectric matrix layer over a support structure. An alternating stack of insulating layers and electrically conductive layers is formed by a series of conformal deposition processes in the cavity and over the dielectric matrix layer. The alternating stack can be planarized employing the top surface of the dielectric matrix layer as a stopping layer. A tip portion of each electrically conductive layer within remaining portions of the alternating stack is laterally offset from the tip of the generally wedge-shaped region by a respective lateral offset distance along a lateral protrusion direction. Contact via structures can be formed on the tip portions of the electrically conductive layers to provide electrical contact.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: May 14, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Michiaki Sano, Zhen Chen, Tetsuya Yamada, Akira Nakada, Yasuke Oda, Manabu Hayashi, Shigenori Sato
  • Patent number: 9731281
    Abstract: A catalyst for hydrocarbon catalytic cracking of the invention contains: a catalyst (a) containing faujasite-type zeolite (A) having a unit cell size in a range of 2.435 nm to 2.455 nm, a matrix component, and rare earths; and a catalyst (b) containing faujasite-type zeolite (B) having a unit cell size in a range of 2.445 nm to 2.462 nm, a matrix component, phosphorus, and magnesium.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: August 15, 2017
    Assignee: JGC CATALYSTS AND CHEMICALS LTD.
    Inventors: Shigenori Hayashi, Seiji Arakawa, Shingo Sakai
  • Publication number: 20150202605
    Abstract: A catalyst for hydrocarbon catalytic cracking of the invention contains: a catalyst (a) containing faujasite-type zeolite (A) having a unit cell size in a range of 2.435 nm to 2.455 nm, a matrix component, and rare earths; and a catalyst (b) containing faujasite-type zeolite (B) having a unit cell size in a range of 2.445 nm to 2.462 nm, a matrix component, phosphorus, and magnesium.
    Type: Application
    Filed: July 12, 2013
    Publication date: July 23, 2015
    Applicant: JGC CATALYSTS AND CHEMICALS LTD.
    Inventors: Shigenori Hayashi, Seiji Arakawa, Shingo Sakai
  • Patent number: 8574972
    Abstract: After a fin-semiconductor region (13) is formed on a substrate (11), impurity-containing gas and oxygen-containing gas are used to perform plasma doping on the fin-semiconductor region (13). This forms impurity-doped region (17) in at least side portions of the fin-semiconductor region (13).
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: November 5, 2013
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Sasaki, Masafumi Kubota, Shigenori Hayashi
  • Patent number: 8216922
    Abstract: Plasma doping is performed using a plasma made of a gas containing an impurity which will serve as a dopant. In this case, at least one of plasma generation high-frequency power and biasing high-frequency power is supplied in the form of pulses.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: July 10, 2012
    Assignee: Panasonic Corporation
    Inventors: Shigenori Hayashi, Masafumi Kubota, Yuichiro Sasaki
  • Publication number: 20120034750
    Abstract: After a fin-semiconductor region (13) is formed on a substrate (11), impurity-containing gas and oxygen-containing gas are used to perform plasma doping on the fin-semiconductor region (13). This forms impurity-doped region (17) in at least side portions of the fin-semiconductor region (13).
    Type: Application
    Filed: October 28, 2010
    Publication date: February 9, 2012
    Inventors: Yuichiro Sasaki, Masafumi Kubota, Shigenori Hayashi
  • Publication number: 20110230038
    Abstract: Plasma doping is performed using a plasma made of a gas containing an impurity which will serve as a dopant. In this case, at least one of plasma generation high-frequency power and biasing high-frequency power is supplied in the form of pulses.
    Type: Application
    Filed: March 18, 2011
    Publication date: September 22, 2011
    Inventors: Shigenori Hayashi, Masafumi Kubota, Yuichiro Sasaki
  • Patent number: 7956413
    Abstract: In a method for manufacturing a semiconductor device having an N-channel field effect transistor, the N-channel field effect transistor is formed by a process including the steps of forming a high dielectric constant gate insulating film on a substrate, forming a gate electrode on the high dielectric constant gate insulating film, forming an extension region by introducing N-type impurities into the substrate by using at least the gate electrode as a mask, and forming a pocket region by introducing P-type impurities under the extension region in the substrate by using at least the gate electrode as a mask. An amount of arsenic (As) that is introduced as the N-type impurities is in a range that is equal to or lower than a prescribed value that is determined based on a thickness of the high dielectric constant gate insulating film.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: June 7, 2011
    Assignee: Panasonic Corporation
    Inventors: Yoshinao Harada, Shigenori Hayashi, Masaaki Niwa
  • Publication number: 20110008954
    Abstract: A semiconductor device includes: an n-transistor including a first gate insulating film made of a high-dielectric-constant material and a first gate electrode fully silicided with a metal, the first gate insulating film and the first gate electrode being formed in this order over a semiconductor region; and a p-transistor including a second gate insulating film made of the high-dielectric-constant material and a second gate electrode fully silicided with the metal, the second gate insulating film and the second gate electrode being formed in this order over the semiconductor region. If the metal has a work function larger than a Fermi level in potential energy of electrons of silicon, a metal concentration of the second gate electrode is higher than that of the first gate electrode whereas if the metal has a work function smaller than the Fermi level of silicon, a metal concentration of the second gate electrode is lower than that of the first gate electrode.
    Type: Application
    Filed: September 13, 2010
    Publication date: January 13, 2011
    Applicants: PANASONIC CORPORATION, IMEC
    Inventors: Shigenori HAYASHI, Riichiro Mitsuhashi
  • Patent number: 7816244
    Abstract: A semiconductor device includes: an n-transistor including a first gate insulating film made of a high-dielectric-constant material and a first gate electrode fully silicided with a metal, the first gate insulating film and the first gate electrode being formed in this order over a semiconductor region; and a p-transistor including a second gate insulating film made of the high-dielectric-constant material and a second gate electrode fully silicided with the metal, the second gate insulating film and the second gate electrode being formed in this order over the semiconductor region. If the metal has a work function larger than a Fermi level in potential energy of electrons of silicon, a metal concentration of the second gate electrode is higher than that of the first gate electrode whereas if the metal has a work function smaller than the Fermi level of silicon, a metal concentration of the second gate electrode is lower than that of the first gate electrode.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: October 19, 2010
    Assignees: Panasonic Corporation, IMEC
    Inventors: Shigenori Hayashi, Riichiro Mitsuhashi
  • Patent number: 7700164
    Abstract: In an apparatus for fabricating a carbon coating, an object such as a magnetic recording medium is disposed on a side of an electrode connected to a high-frequency power supply. Ultrasonic vibrations are supplied to the object. Discharge is generated between the electrode connected to the high-frequency power supply and a grounded electrode to fabricate a carbon coating on the surface of the object. Also, an electrode interval is set to 6 mm or less, pressure between the electrodes is set to 15 Torr to 100 Torr, whereby high-density plasma is generated to form an ion sheath on an anode side. Therefore, a coating is fabricated on the surface of the object by bombardment of ions.
    Type: Grant
    Filed: November 2, 2004
    Date of Patent: April 20, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd
    Inventors: Shunpei Yamazaki, Kenji Itoh, Shigenori Hayashi
  • Publication number: 20090242983
    Abstract: In a method for manufacturing a semiconductor device having an N-channel field effect transistor, the N-channel field effect transistor is formed by a process including the steps of forming a high dielectric constant gate insulating film on a substrate, forming a gate electrode on the high dielectric constant gate insulating film, forming an extension region by introducing N-type impurities into the substrate by using at least the gate electrode as a mask, and forming a pocket region by introducing P-type impurities under the extension region in the substrate by using at least the gate electrode as a mask. An amount of arsenic (As) that is introduced as the N-type impurities is in a range that is equal to or lower than a prescribed value that is determined based on a thickness of the high dielectric constant gate insulating film.
    Type: Application
    Filed: June 4, 2009
    Publication date: October 1, 2009
    Applicant: Panasonic Corporation
    Inventors: Yoshinao HARADA, Shigenori Hayashi, Masaaki Niwa
  • Patent number: 7554156
    Abstract: In a method for manufacturing a semiconductor device having an N-channel field effect transistor, the N-channel field effect transistor is formed by a process including the steps of forming a high dielectric constant gate insulating film on a substrate, forming a gate electrode on the high dielectric constant gate insulating film, forming an extension region by introducing N-type impurities into the substrate by using at least the gate electrode as a mask, and forming a pocket region by introducing P-type impurities under the extension region in the substrate by using at least the gate electrode as a mask. An amount of arsenic (As) that is introduced as the N-type impurities is in a range that is equal to or lower than a prescribed value that is determined based on a thickness of the high dielectric constant gate insulating film.
    Type: Grant
    Filed: October 21, 2005
    Date of Patent: June 30, 2009
    Assignee: Panasonic Corporation
    Inventors: Yoshinao Harada, Shigenori Hayashi, Masaaki Niwa
  • Publication number: 20090130833
    Abstract: A semiconductor device includes: an n-transistor including a first gate insulating film made of a high-dielectric-constant material and a first gate electrode fully silicided with a metal, the first gate insulating film and the first gate electrode being formed in this order over a semiconductor region; and a p-transistor including a second gate insulating film made of the high-dielectric-constant material and a second gate electrode fully silicided with the metal, the second gate insulating film and the second gate electrode being formed in this order over the semiconductor region. If the metal has a work function larger than a Fermi level in potential energy of electrons of silicon, a metal concentration of the second gate electrode is higher than that of the first gate electrode whereas if the metal has a work function smaller than the Fermi level of silicon, a metal concentration of the second gate electrode is lower than that of the first gate electrode.
    Type: Application
    Filed: January 22, 2009
    Publication date: May 21, 2009
    Applicants: PANASONIC CORPORATION, INTERUNIVERSITAIR MICRO-ELEKTRONICA CENTRUM VZW
    Inventors: Shigenori Hayashi, Riichiro Mitsuhashi
  • Patent number: 7495298
    Abstract: A semiconductor device includes: an n-transistor including a first gate insulating film made of a high-dielectric-constant material and a first gate electrode fully silicided with a metal, the first gate insulating film and the first gate electrode being formed in this order over a semiconductor region; and a p-transistor including a second gate insulating film made of the high-dielectric-constant material and a second gate electrode fully silicided with the metal, the second gate insulating film and the second gate electrode being formed in this order over the semiconductor region. If the metal has a work function larger than a Fermi level in potential energy of electrons of silicon, a metal concentration of the second gate electrode is higher than that of the first gate electrode whereas if the metal has a work function smaller than the Fermi level of silicon, a metal concentration of the second gate electrode is lower than that of the first gate electrode.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: February 24, 2009
    Assignees: Panasonic Corporation, Interuniversitair Micro-Elektronica Centrum VZW
    Inventors: Shigenori Hayashi, Riichiro Mitsuhashi
  • Patent number: 7488655
    Abstract: A metal film is deposited on a silicon region in a non-oxidizing atmosphere, after which the metal film is oxidized with radicals capable of oxidizing the metal film, such as oxygen radicals, to form a metal oxide film serving as a gate insulating film.
    Type: Grant
    Filed: January 14, 2004
    Date of Patent: February 10, 2009
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shigenori Hayashi, Kazuhiko Yamamoto
  • Patent number: 7465618
    Abstract: A semiconductor device includes: a semiconductor substrate; a gate insulating film formed on the semiconductor substrate and made of a high-dielectric-constant material composed of a plurality of layers stacked perpendicularly to a principal surface of the semiconductor substrate and associated with respective phases; and a gate electrode formed on the gate insulating film.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: December 16, 2008
    Assignees: Panasonic Corporation, Interuniversitair Micro-Elektronica Centrum VZW
    Inventors: Shigenori Hayashi, Kazuhiko Yamamoto