Abstract: A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed above the semiconductor substrate, traversing the p-MOS active region and defining a p-MOS channel region under the p-MOS gate electrode structure; a compressive stress film selectively formed above the p-MOS active region and covering the p-MOS gate electrode structure; and a stress released region selectively formed above the element isolation region in the p-MOS region and releasing stress in the compressive stress film, wherein a compressive stress along the gate length direction and a tensile stress along the gate width direction are exerted on the p-MOS channel region. The performance of the semiconductor device can be improved by controlling the stress separately for the active region and element isolation region.

Abstract: A trench is formed in a surface layer of a semiconductor substrate, the trench surrounding an active region. A lower insulating film made of insulating material is deposited over the semiconductor device, the lower insulating film filling a lower region of the trench and leaving an empty space in an upper region. An upper insulating film made of insulating material having therein a tensile stress is deposited on the lower insulating film, the upper insulating film filling the empty space left in the upper space. The upper insulating film and the lower insulating film deposited over the semiconductor substrate other than in the trench are removed.

Abstract: A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area.

Abstract: A method of manufacturing a semiconductor device includes forming a first and a second isolation insulating film to define a first, a second, a third and a fourth region, forming a first insulating film, implanting a first impurity of a first conductivity type through the first insulating film into the first, the second and the fourth region at a first depth, forming a second insulating film thinner than the first insulating film, implanting a second impurity of a second conductivity type through the second insulating film into the third region at a second depth in the semiconductor substrate, implanting a third impurity of the second conductivity type into the third region at a third depth shallower than the second depth, forming a first transistor of the first conductivity type in the third region, and forming a second transistor of the second conductivity type in the fourth region.

Abstract: A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed above the semiconductor substrate, traversing the p-MOS active region and defining a p-MOS channel region under the p-MOS gate electrode structure; a compressive stress film selectively formed above the p-MOS active region and covering the p-MOS gate electrode structure; and a stress released region selectively formed above the element isolation region in the p-MOS region and releasing stress in the compressive stress film, wherein a compressive stress along the gate length direction and a tensile stress along the gate width direction are exerted on the p-MOS channel region. The performance of the semiconductor device can be improved by controlling the stress separately for the active region and element isolation region.

Abstract: A semiconductor device is provided with a first conductivity type semiconductor substrate (10); a voltage supplying terminal (26) arranged on the semiconductors substrate (10); one or more elements (6) which include a second conductivity type well section (22) and are arranged on the semiconductor substrate (10); a second conductivity type first conductive layer (21), which is a lower layer of the one or more elements (6), is in contact with the second conductivity type well section (22), and connects the second conductivity type well section (22) of the one or more elements (6) with the voltage supplying terminal (26); and a first conductivity type second conductive layer (11) formed in contact with a lower side of the first conductive layer (21).

Abstract: A trench is formed in a surface layer of a semiconductor substrate, the trench surrounding an active region. A lower insulating film made of insulating material is deposited over the semiconductor device, the lower insulating film filling a lower region of the trench and leaving an empty space in an upper region. An upper insulating film made of insulating material having therein a tensile stress is deposited on the lower insulating film, the upper insulating film filling the empty space left in the upper space. The upper insulating film and the lower insulating film deposited over the semiconductor substrate other than in the trench are removed.

Abstract: A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed above the semiconductor substrate, traversing the p-MOS active region and defining a p-MOS channel region under the p-MOS gate electrode structure; a compressive stress film selectively formed above the p-MOS active region and covering the p-MOS gate electrode structure; and a stress released region selectively formed above the element isolation region in the p-MOS region and releasing stress in the compressive stress film, wherein a compressive stress along the gate length direction and a tensile stress along the gate width direction are exerted on the p-MOS channel region. The performance of the semiconductor device can be improved by controlling the stress separately for the active region and element isolation region.

Abstract: A trench is formed in the surface layer of a semiconductor substrate, surrounding an active region. A lower insulating film made of insulating material fills a lower region of the trench. An upper insulating film fills a region of the trench above the lower insulating film. The upper insulating film has therein a stress generating tensile strain in a surface layer of the active region.

Abstract: A first well is formed in the surface layer of a semiconductor substrate, the first layer being of a first conductivity type, the first well being of a second conductivity type opposite to the first conductivity type. A pair of current input/output ports are connected to the first well, the pair of current input/output ports being used for flowing current through the first well along the direction parallel to a substrate surface. A second well of the first conductivity type is disposed between the pair of current input/output ports, the second well being shallower than the first well. A resistor element is provided which facilitates to have a desired resistance value.

Abstract: A semiconductor device is disclosed that includes a semiconductor substrate, a device region disposed at a predetermined location of the semiconductor substrate, and a shallow trench isolation region that isolates the device region. The shallow trench isolation region includes a trench, a nitride film liner disposed at an upper portion of a side wall of the trench, and a thermal oxide film disposed at a lower portion of the side wall of the trench. The shallow trench isolation is arranged such that the width of a second portion of the shallow trench isolation region at which the thermal oxide film is disposed may be wider than the width of a first portion of the shallow trench isolation region at which the lower end of the nitride film liner is disposed.

Abstract: A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed above the semiconductor substrate, traversing the p-MOS active region and defining a p-MOS channel region under the p-MOS gate electrode structure; a compressive stress film selectively formed above the p-MOS active region and covering the p-MOS gate electrode structure; and a stress released region selectively formed above the element isolation region in the p-MOS region and releasing stress in the compressive stress film, wherein a compressive stress along the gate length direction and a tensile stress along the gate width direction are exerted on the p-MOS channel region. The performance of the semiconductor device can be improved by controlling the stress separately for the active region and element isolation region.

Abstract: A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed above the semiconductor substrate, traversing the p-MOS active region and defining a p-MOS channel region under the p-MOS gate electrode structure; a compressive stress film selectively formed above the p-MOS active region and covering the p-MOS gate electrode structure; and a stress released region selectively formed above the element isolation region in the p-MOS region and releasing stress in the compressive stress film, wherein a compressive stress along the gate length direction and a tensile stress along the gate width direction are exerted on the p-MOS channel region. The performance of the semiconductor device can be improved by controlling the stress separately for the active region and element isolation region.

Abstract: A semiconductor device is provided with a first conductivity type semiconductor substrate (10); a voltage supplying terminal (26) arranged on the semiconductors substrate (10); one or more elements (6) which include a second conductivity type well section (22) and are arranged on the semiconductor substrate (10); a second conductivity type first conductive layer (21), which is a lower layer of the one or more elements (6), is in contact with the second conductivity type well section (22), and connects the second conductivity type well section (22) of the one or more elements (6) with the voltage supplying terminal (26); and a first conductivity type second conductive layer (11) formed in contact with a lower side of the first conductive layer (21).

Abstract: A semiconductor device includes a semiconductor substrate. A gate electrode is formed on the semiconductor substrate via a gate insulating film. A source region and a drain region of a first conductivity type are formed on the first side and the second side of the gate electrode, respectively, in the semiconductor substrate. A punch-through stopper region of a second conductivity type is formed in the semiconductor substrate such that the second conductivity type punch-through stopper region is located between the source region and the drain region at distances from the source region and the drain region and extends in the direction perpendicular to the principal surface of the semiconductor substrate. The concentration of an impurity element of the second conductivity type in the punch-through stopper region is set to be at least five times the substrate impurity concentration between the source region and the drain region.

Abstract: A trench is formed in the surface layer of a semiconductor substrate, surrounding an active region. A lower insulating film made of insulating material fills a lower region of the trench. An upper insulating film fills a region of the trench above the lower insulating film. The upper insulating film has therein a stress generating tensile strain in a surface layer of the active region.

Abstract: An impurity having a conductivity type same as that contained in a source-and-drain region is implanted to an exposed surface of a gate electrode along a direction inclined to the surface of said semiconductor substrate, while using over-etched sidewalls as a mask, where the gate electrode is implanted both at the top surface and the upper portion of one side face thereof, whereas one of the source-and-drain regions is implanted with the impurity in an amount possibly attained by a single implantation, but the other portion is not implanted or only slightly implanted to a less affective degree.

Abstract: A semiconductor device includes a semiconductor substrate. A gate electrode is formed on the semiconductor substrate via a gate insulating film. A source region and a drain region of a first conductivity type are formed on the first side and the second side of the gate electrode, respectively, in the semiconductor substrate. A punch-through stopper region of a second conductivity type is formed in the semiconductor substrate such that the second conductivity type punch-through stopper region is located between the source region and the drain region at distances from the source region and the drain region and extends in the direction perpendicular to the principal surface of the semiconductor substrate. The concentration of an impurity element of the second conductivity type in the punch-through stopper region is set to be at least five times the substrate impurity concentration between the source region and the drain region.

Abstract: A semiconductor device is disclosed that includes a semiconductor substrate, a device region disposed at a predetermined location of the semiconductor substrate, and a shallow trench isolation region that isolates the device region. The shallow trench isolation region includes a trench, a nitride film liner disposed at an upper portion of a side wall of the trench, and a thermal oxide film disposed at a lower portion of the side wall of the trench. The shallow trench isolation is arranged such that the width of a second portion of the shallow trench isolation region at which the thermal oxide film is disposed may be wider than the width of a first portion of the shallow trench isolation region at which the lower end of the nitride film liner is disposed.

Abstract: A semiconductor device includes a semiconductor substrate. A gate electrode is formed on the semiconductor substrate via a gate insulating film. A source region and a drain region of a first conductivity type are formed on the first side and the second side of the gate electrode, respectively, in the semiconductor substrate. A punch-through stopper region of a second conductivity type is formed in the semiconductor substrate such that the second conductivity type punch-through stopper region is located between the source region and the drain region at distances from the source region and the drain region and extends in the direction perpendicular to the principal surface of the semiconductor substrate. The concentration of an impurity element of the second conductivity type in the punch-through stopper region is set to be at least five times the substrate impurity concentration between the source region and the drain region.