Patents by Inventor Shigeo Satoh

Shigeo Satoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7060578
    Abstract: An impurity having a conductivity type same as that contained in a source-and-drain region is implanted to an exposed surface of a gate electrode along a direction inclined to the surface of said semiconductor substrate, while using over-etched sidewalls as a mask, where the gate electrode is implanted both at the top surface and the upper portion of one side face thereof, whereas one of the source-and-drain regions is implanted with the impurity in an amount possibly attained by a single implantation, but the other portion is not implanted or only slightly implanted to a less affective degree.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: June 13, 2006
    Assignee: Fujitsu Limited
    Inventors: Shigeo Satoh, Masataka Kase
  • Publication number: 20060091473
    Abstract: A semiconductor device includes a semiconductor substrate. A gate electrode is formed on the semiconductor substrate via a gate insulating film. A source region and a drain region of a first conductivity type are formed on the first side and the second side of the gate electrode, respectively, in the semiconductor substrate. A punch-through stopper region of a second conductivity type is formed in the semiconductor substrate such that the second conductivity type punch-through stopper region is located between the source region and the drain region at distances from the source region and the drain region and extends in the direction perpendicular to the principal surface of the semiconductor substrate. The concentration of an impurity element of the second conductivity type in the punch-through stopper region is set to be at least five times the substrate impurity concentration between the source region and the drain region.
    Type: Application
    Filed: December 15, 2005
    Publication date: May 4, 2006
    Applicant: Fujitsu Limited
    Inventors: Taketo Watanabe, Toshio Nomura, Shinichi Kawai, Takayuki Kawamata, Shigeo Satoh
  • Patent number: 7034366
    Abstract: A semiconductor device includes a semiconductor substrate. A gate electrode is formed on the semiconductor substrate via a gate insulating film. A source region and a drain region of a first conductivity type are formed on the first side and the second side of the gate electrode, respectively, in the semiconductor substrate. A punch-through stopper region of a second conductivity type is formed in the semiconductor substrate such that the second conductivity type punch-through stopper region is located between the source region and the drain region at distances from the source region and the drain region and extends in the direction perpendicular to the principal surface of the semiconductor substrate. The concentration of an impurity element of the second conductivity type in the punch-through stopper region is set to be at least five times the substrate impurity concentration between the source region and the drain region.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: April 25, 2006
    Assignee: Fujitsu Limited
    Inventors: Taketo Watanabe, Toshio Nomura, Shinichi Kawai, Takayuki Kawamata, Shigeo Satoh
  • Publication number: 20050285137
    Abstract: A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed above the semiconductor substrate, traversing the p-MOS active region and defining a p-MOS channel region under the p-MOS gate electrode structure; a compressive stress film selectively formed above the p-MOS active region and covering the p-MOS gate electrode structure; and a stress released region selectively formed above the element isolation region in the p-MOS region and releasing stress in the compressive stress film, wherein a compressive stress along the gate length direction and a tensile stress along the gate width direction are exerted on the p-MOS channel region. The performance of the semiconductor device can be improved by controlling the stress separately for the active region and element isolation region.
    Type: Application
    Filed: October 22, 2004
    Publication date: December 29, 2005
    Applicant: FUJITSU LIMITED
    Inventor: Shigeo Satoh
  • Publication number: 20050287756
    Abstract: A first well is formed in the surface layer of a semiconductor substrate, the first layer being of a first conductivity type, the first well being of a second conductivity type opposite to the first conductivity type. A pair of current input/output ports are connected to the first well, the pair of current input/output ports being used for flowing current through the first well along the direction parallel to a substrate surface. A second well of the first conductivity type is disposed between the pair of current input/output ports, the second well being shallower than the first well. A resistor element is provided which facilitates to have a desired resistance value.
    Type: Application
    Filed: September 28, 2004
    Publication date: December 29, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Kaina Suzuki, Shigeo Satoh
  • Publication number: 20040065926
    Abstract: A semiconductor device includes a semiconductor substrate. A gate electrode is formed on the semiconductor substrate via a gate insulating film. A source region and a drain region of a first conductivity type are formed on the first side and the second side of the gate electrode, respectively, in the semiconductor substrate. A punch-through stopper region of a second conductivity type is formed in the semiconductor substrate such that the second conductivity type punch-through stopper region is located between the source region and the drain region at distances from the source region and the drain region and extends in the direction perpendicular to the principal surface of the semiconductor substrate. The concentration of an impurity element of the second conductivity type in the punch-through stopper region is set to be at least five times the substrate impurity concentration between the source region and the drain region.
    Type: Application
    Filed: August 5, 2003
    Publication date: April 8, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Taketo Watanabe, Toshio Nomura, Shinichi Kawai, Takayuki Kawamata, Shigeo Satoh
  • Publication number: 20040041177
    Abstract: An impurity having a conductivity type same as that contained in a source-and-drain region is implanted to an exposed surface of a gate electrode along a direction inclined to the surface of said semiconductor substrate, while using over-etched sidewalls as a mask, where the gate electrode is implanted both at the top surface and the upper portion of one side face thereof, whereas one of the source-and-drain regions is implanted with the impurity in an amount possibly attained by a single implantation, but the other portion is not implanted or only slightly implanted to a less affective degree.
    Type: Application
    Filed: August 27, 2003
    Publication date: March 4, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Shigeo Satoh, Masataka Kase
  • Patent number: 5229219
    Abstract: According to the invention, a magnetic recording medium is formed by using magnetic powder having a composition of the following formula:MeO.multidot.n[Fe.sub.2-x-y-z Ga.sub.x Cr.sub.y Al.sub.z O.sub.3 ]wherein Me is at least on element selected from the group consisting of Ba, Sr, Pb, and Ca,4.5.ltoreq.n.ltoreq.6, x.gtoreq.0, y.gtoreq.0, z.gtoreq.0,x/3+y/4+z/6.gtoreq.1/6, andx/6+y/10+z/11.ltoreq.1/6,preferably the number of those particles having a particle size of from 0.5d to 1.5d being at least 65% of the entire particles wherein is an average particle size, and the Fe content on the particle surface being substantially equal to the Fe content in the particle interior, and blending the powder with a binder. Thermomagnetic recording and thermomagnetic duplication are carried out using the medium. There results a magnetic layer which has high Hc, is not easily erased once recorded, has high squareness ratio, and enables thermomagnetic recording and thermomagnetic duplication at 100.degree. to 180.degree. C.
    Type: Grant
    Filed: July 9, 1990
    Date of Patent: July 20, 1993
    Assignee: TDK Corporation
    Inventors: Hideharu Moro, Shigeo Satoh, Osamu Kohmoto, Tetsuhito Yoneyama, Shohei Mimura, Haruyuki Takahashi, Atsushi Makimura
  • Patent number: 5018363
    Abstract: An apparatus for preparing ice creams, wherein a freezing cylinder is constituted such that a liquid mix supplied from a mix tank is stirred in a stirring apparatus that is installed in the inside of the freezing cylinder, and refrigerated so as to complete ice creams, any amount of which can be dispensed through a dispensing port. For the cleaning and sterilization of the inside of the cylinder, the inside is heated by reversing the flow of heat media which are to be circulated through the refrigerating part of the cylinder to dissolve and automatically withdraw the ice creams in the cylinder, then cleaned several times by supplying and discharging hot water, to and from the inside, and after that sterilized by supplying hot water to the inside, and discharging the water from it.
    Type: Grant
    Filed: June 19, 1989
    Date of Patent: May 28, 1991
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ken Aoki, Katsuhiko Hoshi, Shigeo Satoh, Mitsuru Kakinuma, Shigeru Togashi, Hiromi Saitoh
  • Patent number: 4860550
    Abstract: An apparatus for preparing ice creams, wherein a freezing cylinder is constituted such that a liquid mix supplied from a mix tank is stirred in a stirring apparatus that is installed in the inside of the freezing cylinder, and refrigerated so as to complete ice creams, any amount of which can be dispensed through a dispensing port. For the cleaning and sterilization of the inside of the cylinder, the inside is heated by reversing the flow of heat media which are to be circulated through the refrigerating part of the cylinder to dissolve and automatically withdraw the ice creams in the cylinder, then cleaned several times by supplying and discharging hot water, to and from the inside, and after that sterilized by supplying hot water to the inside, and discharging the water from it.
    Type: Grant
    Filed: August 8, 1988
    Date of Patent: August 29, 1989
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ken Aoki, Katsuhiko Hoshi, Shigeo Satoh, Mitsuru Kakinuma, Shigeru Togashi, Hiromi Saitoh
  • Patent number: 4703628
    Abstract: An apparatus for preparing frozen products having a mix tank, a freezing chamber, a liquid mix supply means, a dispensing device, a freezing means for the freezing chamber comprising independent first and second freezing systems, and a frozen control means comprising a first and second frozen control means for said first and second freezing systems respectively, and making it possible that liquid mix in the freezing chamber may be always frozen in good condition. Further an apparatus for preparing frozen products having a frozen and chilled control means for the freezing means independently, and making it possible that liquid mix is stored in the freezing chamber when the freezing operation does not occur.
    Type: Grant
    Filed: August 7, 1985
    Date of Patent: November 3, 1987
    Assignee: Sanyo Electric Co.
    Inventors: Shigeru Togashi, Hiromi Saitoh, Shigeyuki Takahashi, Yasuo Makino, Mitsuru Kakinuma, Shigeo Satoh, Shigeki Sugiyama