Abstract: A semiconductor device at least has a memory cell array. The memory cell array has active regions extending linearly in parallel with one another at predetermined intervals and each containing alternating source and drain regions, gate electrodes orthogonally crossing the active regions between the source and drain regions and each having a floating gate and a control gate laid one upon another, first conductors extending linearly in parallel with the gate electrodes and connected to corresponding ones of the source regions through source contacts, and second conductors connected to corresponding ones of the drain regions through drain contacts.

Abstract: In a channel-erase EEPROM, there is a parasitic capacitance between node N1 to which a substrate voltage is supplied and node N2 to which the voltage on a word line is supplied. A negative voltage is applied to the word line in erasing the data in a memory cell. A switch circuit SW1 is connected between node N1 and node N2. Between node N1 and the ground, a switch SW4 is connected. A switch SW5 is connected between node N2 and the ground. When the erase operation has been completed, the switch circuit SW1 is first turned on, short-circuiting node N1 and node N2. Thereafter, the switch circuits SW4, SW5 are turned on, grounding node N1 and node N2 separately.

Abstract: There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.

Abstract: A first address subset is allocated as a first column address in a nonvolatile semiconductor memory. In addition, a second address subset higher in order than the first address subset is allocated as a first row address. Furthermore, a third address subset higher in order than the second address subset is allocated as a second column address.

Abstract: There is disclosed a semiconductor integrated circuit device comprising a memory cell array, row decoder, sense amplifier, column gate with two or more stages connected in series, column gate driving circuit, data latch, multiplexer, and address control circuit, and the multiplexer sequentially selects data corresponding to a predetermined address from a plurality of data latched by the data latch. The address control circuit reverses a driving signal for driving at least one stage of the column gate with two or more stages connected in series and selects the columns designated by the next selected plurality of addresses, while the multiplexer sequentially selects the data corresponding to the predetermined address.

Abstract: A semiconductor memory device comprises memory cell blocks, a first redundancy cell array for each of the memory blocks, a redundancy cell block, a second redundancy cell array for the redundancy block, a first defect rescuing circuit configured to output a replacement signal for replacing a defective cell array in the redundancy block with the first redundancy array, and a second defect rescuing circuit configured to output a replacement signal for replacing a defective memory block with the redundancy block, wherein the first defect rescuing circuit has a gate circuit which outputs the output replacement signal of the first address sensing circuit as valid at an address at which the second defect rescuing circuit is not implemented, and which outputs a signal indicating which block is a defective block outputted by the second defect rescuing circuit as valid at an address at which the second defect rescuing circuit is implemented.

Abstract: There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.

Abstract: A nonvolatile semiconductor memory includes first and second nonvolatile memory banks, a data-line for read, a data-line for program and verify, a sense amplifier for read, a sense amplifier for program and verify, and a program circuit. The data-lines are arranged in a region between the first and second nonvolatile memory banks, and selectively connected to the bit-lines of the first and second nonvolatile memory banks. The sense amplifier for read is connected to the data-line for read. The sense amplifier for program and verify and the program circuit are connected to the data-line for program and verify.

Abstract: In a channel-erase EEPROM, there is a parasitic capacitance between node N1 to which a substrate voltage is supplied and node N2 to which the voltage on a word line is supplied. A negative voltage is applied to the word line in erasing the data in a memory cell. A switch circuit SW1 is connected between node N1 and node N2. Between node N1 and the ground, a switch SW4 is connected. A switch SW5 is connected between node N2 and the ground. When the erase operation has been completed, the switch circuit SW1 is first turned on, short-circuiting node N1 and node N2. Thereafter, the switch circuits SW4, SW5 are turned on, grounding node N1 and node N2 separately.

Abstract: A nonvolatile semiconductor memory device comprises a first memory cell array including electrically re-programmable main memory cells, a second memory cell array including electrically data-programmable redundancy memory cells, a first storage configured to store a specified code, a first comparator configured to compare a selected code with the specified code to generate an activating signal, a faulty address latch circuit configured to be activated by the activating signal and controlled to temporarily latch a fault address corresponding to the fault, a second storage configured to store the faulty address latched by the faulty address latch circuit, a second comparator configured to compare an input address with the faulty address to generate a replacement control signal when the input address coincides with the faulty address, and a replacing circuit configured to replace an output of the first memory cell array with an output of the second memory cell array.

Abstract: A nonvolatile semiconductor memory device includes a row decoder circuit having first and second N-channel MOS transistors and first and second P-channel MOS transistors which correspond to each of word lines. One end of a source-to-drain current path of the first N-channel MOS transistor is connected to the word line, and the other end thereof is connected to a corresponding one of output terminals of a predecoder circuit. One end of a source-to-drain current path of the second N-channel MOS transistor is connected to the word line, and the other end thereof is supplied with a voltage of OV or more in a data erase mode and is supplied with a low logical level signal in modes other than the data erase mode.

Abstract: There is disclosed a semiconductor integrated circuit device comprising a memory cell array, row decoder, sense amplifier, column gate with two or more stages connected in series, column gate driving circuit, data latch, multiplexer, and address control circuit, and the multiplexer sequentially selects data corresponding to a predetermined address from a plurality of data latched by the data latch. The address control circuit reverses a driving signal for driving at least one stage of the column gate with two or more stages connected in series and selects the columns designated by the next selected plurality of addresses, while the multiplexer sequentially selects the data corresponding to the predetermined address.

Abstract: A semiconductor device has an address counter to output, in a first mode, a first block address whereas, in a second mode, a second block address selected from a block-address space two times larger than a block-address space corresponding to memory blocks, the memory blocks and at least one redundant block being included in a memory section, and a block-selection controller, in the second mode, one of the memory blocks, which corresponds to the output of the address counter, when the most significant value of the second block address as the output of the address counter is at a first level whereas select the redundant block while the memory blocks are inhibited from selection, when the most significant value is at a second level.

Abstract: In a flash memory EEPROM, a memory cell MC is formed in a P-type semiconductor substrate. A peripheral transistor TR is formed in an N-type well. Another peripheral transistor TR is formed in a P-type well. The P-type well is by turn formed an N-type well and electrically insulated from the substrate. The substrate is typically provided with a metal back structure and its substrate voltage is set to predetermined voltages respectively for data erasure, data storage and data retrieval. With such an arrangement, the level of voltage stress with which the device is loaded during data erasure can be remarkably reduced to allow a down-sizing and an enhanced quality to be realized for the device.

Abstract: A semiconductor integrated circuit device comprises an integrated circuit provided in a semiconductor chip and setting information memory. The setting information memory stores operation/function setting information of the integrated circuit and receives a signal generated based on power-on in reading out the operation/function setting information.

Abstract: A voltage-level shifter has a first and a second power supply terminal to which a first and a second potential are supplied, respectively, the second potential being lower than the first potential; a first input terminal to which a first input signal is supplied, the first input signal having a high and a low level according to the first and the second potentials; a second input terminal to which a second input signal is supplied, the second input signal being an inverted signal of the first input signal.

Abstract: A number of booster circuits to be operated out of a plurality of booster circuits are selected in accordance with a level of the boosted voltage to be provided at a common voltage output terminal of the plurality of booster circuits. With such an arrangement, fluctuations in the output voltage that can appear when a light load is applied to the voltage output terminal of the booster circuits can be effectively reduced to make the semiconductor memory device driven by the power supply circuit operate reliably. Further, one of the output terminals of intermediate voltage booster circuits is connected to the output terminal of a high voltage booster circuit. Then, a desired voltage can be obtained from the booster circuits that are implemented without using costly transistors to reduce the chip cost.

Abstract: A semiconductor memory device comprising first memory blocks, a first decoder, at least one second memory block, a second decoder, a defective block address storing section, and a block address comparing section. The second memory block has substantially the same construction as the first memory blocks. The defective address storing section has a memory element and stores a defective block address. A readout operation of the defective block address storing section is effected at the turn-ON time of a power supply. The block address comparing section compares the defective block address stored in the defective block address storing section with an input block address. The first decoder which selects the first memory block in which a defective cell occurs is set into the non-selected state and the second decoder is set into selected state when coincidence of the compared address is detected in the block address comparing section.

Abstract: In a channel-erase EEPROM, there is a parasitic capacitance between node N1 to which a substrate voltage is supplied and node N2 to which the voltage on a word line is supplied. A negative voltage is applied to the word line in erasing the data in a memory cell. A switch circuit SW1 is connected between node N1 and node N2. Between node N1 and the ground, a switch SW4 is connected. A switch SW5 is connected between node N2 and the ground. When the erase operation has been completed, the switch circuit SW1 is first turned on, short-circuiting node N1 and node N2. Thereafter, the switch circuits SW4, SW5 are turned on, grounding node N1 and node N2 separately.

Abstract: In a channel-erase EEPROM, there is a parasitic capacitance between node N1 to which a substrate voltage is supplied and node N2 to which the voltage on a word line is supplied. A negative voltage is applied to the word line in erasing the data in a memory cell. A switch circuit SW1 is connected between node N1 and node N2. Between node N1 and the ground, a switch SW4 is connected. A switch SW5 is connected between node N2 and the ground. When the erase operation has been completed, the switch circuit SW1 is first turned on, short-circuiting node N1 and node N2. Thereafter, the switch circuits SW4, SW5 are turned on, grounding node N1 and node N2 separately.