Abstract: A nonvolatile semiconductor memory device includes a row decoder circuit having first and second N-channel MOS transistors and first and second P-channel MOS transistors which correspond to each of word lines. One end of a source-to-drain current path of the first N-channel MOS transistor is connected to the word line, and the other end thereof is connected to a corresponding one of output terminals of a predecoder circuit. One end of a source-to-drain current path of the second N-channel MOS transistor is connected to the word line, and the other end thereof is supplied with a voltage of 0 V or more in a data erase mode and is supplied with a low logical level signal in modes other than the data erase mode.

Abstract: A high voltage generator circuit comprises a boosting circuit, limiter circuit, and a bypass circuit. When a supply voltage is inputted into the boosting circuit, a high voltage is generated and supplied to the limiter circuit. When the high voltage generated by the boosting circuit exceeds a limit voltage of the limiter circuit, the limiter circuit operates and the output voltage of the boosting circuit is thus maintained at a constant value. When the output voltage exceeds the limit voltage of the limiter circuit and an output current of the boosting circuit exceeds a reference value, a portion of the output current of the boosting circuit equivalent to a difference between the output current and a predetermined value is bypassed and discharged by the bypass circuit stated above.

Abstract: In a flash memory EEPROM, a memory cell MC is formed in a P-type semiconductor substrate. A peripheral transistor TR is formed in an N-type well. Another peripheral transistor TR is formed in a P-type well. The P-type well is by turn formed an N-type well and electrically insulated from the substrate. The substrate is typically provided with a metal back structure and its substrate voltage is set to predetermined voltages respectively for data erasure, data storage and data retrieval. With such an arrangement, the level of voltage stress with which the device is loaded during data erasure can be remarkably reduced to allow a down-sizing and an enhanced quality to be realized for the device.

Abstract: A nonvolatile semiconductor memory device is provided in which a negative voltage is applied to a gate electrode of a memory cell transistor during an erase mode. The memory device includes a row decoder circuit having an N-channel transistor connected to a word line. The N-channel transistor is provided on a P-type well region of a semiconductor substrate. A negative voltage is applied to the P-type well region during the erase mode, while ground potential is applied thereto during other modes.

Abstract: A nonvolatile semiconductor memory device is provided in which a negative voltage is applied to a gate electrode of a memory cell transistor during an erase mode. The memory device includes a row decoder circuit having an N-channel transistor connected to a word line. The N-channel transistor is provided on a P-type well region of a semiconductor substrate. A negative voltage is applied to the P-type well region during the erase mode, while ground potential is applied thereto during other modes.

Abstract: A high voltage generator circuit comprises a boosting circuit, limiter circuit, and a bypass circuit. When a supply voltage is inputted into the boosting circuit a high voltage is generated and supplied to the limiter circuit. When the high voltage generated by the boosting circuit exceeds a limit voltage of the limiter circuit, the limiter circuit operates and the output voltage of the boosting circuit is thus maintained at a constant value. When the output voltage exceeds the limit voltage of the limiter circuit and an output current of the boosting circuit exceeds a reference value, a portion of the output current of the boosting circuit equivalent to a difference between the output current and a predetermined value is bypassed and discharged by the bypass circuit stated above.

Abstract: In a flash memory EEPROM, a memory cell MC is formed in a P-type semiconductor substrate. A peripheral transistor TR is formed in an N-type well. Another peripheral transistor TR is formed in a P-type well. The P-type well is by turn formed an N-type well and electrically insulated from the substrate. The substrate is typically provided with a metal back structure and its substrate voltage is set to predetermined voltages respectively for data erasure, data storage and data retrieval with such an arrangement, the level of voltage stress with which the device is loaded during data erasure can be remarkably reduced to allow a down-sizing and an enhanced quality to be realized for the device.

Abstract: A memory cell array has a plurality of memory cells formed of EEPROM cells arranged in a matrix form. Data in the memory cells is flash-erased, and after this, word lines other than a selected word line are set to a negative potential and erasing verification for detecting an insufficiently erased memory cell is effected. The flash-erasing and erasing verification are repeatedly effected until no insufficiently erased memory cell is detected. When no insufficiently erased memory cell is detected, word lines other than a selected word line are set to a negative potential and an overerased memory cell is detected. When an overerased memory cell is detected, weak program is effected for the cell by applying a voltage lower than the normal writing voltage to the cell.

Abstract: In a nonvolatile semiconductor memory having a two-stage sense read circuit using a level shift circuit and a single-end sense amplifier, relationships of sizes of a main memory cell bit line charge transistor, a main memory cell bit line transfer gate transistor, a main memory cell bit line load transistor, a dummy cell bit line charge transistor, a dummy cell bit line transfer gate transistor, and a dummy cell bit line load transistor are set to simultaneously satisfy conditions for equalizing a bit line and a dummy cell bit line and conditions for equalizing a sense line and a dummy cell sense line. Therefore, the potentials of the bit line and the dummy cell bit line and the potentials of the sense line and the dummy cell sense line can be simultaneously equalized, and a high-speed read operation can be achieved.

Abstract: A nonvolatile semiconductor memory device is provided in which a negative voltage is applied to a gate electrode of a memory cell transistor during an erase mode. The memory device includes a row decoder circuit having an N-channel transistor connected to a word line. The N-channel transistor is provided on a P-type well region of a semiconductor substrate. A negative voltage is applied to the P-type well region during the erase mode, while ground potential is applied thereto during other modes.

Abstract: In a flash memory EEPROM, a memory cell MC is formed in a P-type semiconductor substrate. A peripheral transistor TR is formed in an N-type well. Another peripheral transistor TR is formed in a P-type well. The P-type well is by turn formed an N-type well and electrically insulated from the substrate. The substrate is typically provided with a metal back structure and its substrate voltage is set to predetermined voltages respectively for data erasure, data storage and data retrieval. With such an arrangement, the level of voltage stress with which the device is loaded during data erasure can be remarkably reduced to allow a down-sizing and an enhanced quality to be realized for the device.

Abstract: A data latch circuit comprises a non-volatile memory cell having its threshold voltage changed in accordance with data to be stored therein, and a latch circuit. The cell has a transistor for writing data and a transistor for reading data. The writing and reading transistors has a common floating gate. The reading transistor has a threshold voltage lower than the writing transistor. During normal operation, a ground potential is applied to the control gate of the reading transistor. The latch circuit latches data in accordance with whether the non-volatile memory cell is in the on-state or off-state.

Abstract: A boosting circuit generates an internal high voltage of a level higher than that of an internal voltage which is used in a semiconductor memory device. The boosting circuit has an output end connected to a capacitor having a large capacitance, and this capacitor is charged to an internal high voltage. The output end of the boosting circuit is connected to a drain of an N-channel transistor. This transistor has a gate which is supplied with a voltage V.sub.G higher than the internal voltage by a difference equivalent to a threshold voltage of the transistor. The internal voltage is outputted from a source of the transistor. When a skew occurs and the internal voltage is lowered while an address signal is changed, the internal high voltage charged in the capacitor is discharged through the transistor and the internal voltage is thus stabilized.

Abstract: A nonvolatile semiconductor memory device is provided in which a negative voltage is applied to a gate electrode of a memory cell transistor during an erase mode. The memory device includes a row decoder circuit having an N-channel transistor connected to a word line. The N-channel transistor is provided on a P-type well region of a semiconductor substrate. A negative voltage is applied to the P-type well region during the erase mode, while ground potential is applied thereto during another modes.

Abstract: This invention, which relates to the output circuit of a sense amplifier that amplifies the signal read from the memory, maintains the output signal stably at a specified level in the presence of equalize pulse signals. Differential amplifiers (36a, 36b) amplify a pair of complementary signals read from the memory. The output terminals of these differential amplifiers (36a, 36b) are connected to each other by transfer gates (N1, P1) controlled by the equalize pulse signals (EQ, /EQ) and also connected to latch circuits (13, 14) via clocked inverter circuits (11, 12). The clocked inverter circuits (11, 12) are put in a high impedance state during the presence of the equalize pulse signals, so that the signals held in the latch circuits (13, 14) remain unchanged.

Abstract: A data latch circuit comprises a non-volatile memory cell having its threshold voltage changed in accordance with data to be stored therein, and a latch circuit. The cell has a transistor for writing data and a transistor for reading data. The writing and reading transistors has a common floating gate. The reading transistor has a threshold voltage lower than the writing transistor. During normal operation, a ground potential is applied to the control gate of the reading transistor. The latch circuit latches data in accordance with whether the non-volatile memory cell is in the on-state or off-state.

Abstract: This invention provides a semiconductor memory device comprising a plurality of memory cells having a common source diffused region extending in a specified direction, a word line that extends in parallel with the common source diffused region and is connected to each gate of the plurality of memory cells, a first source interconnection composed of a first metal interconnection layer electrically connected to the common source diffused region, and a second source interconnection that extends in parallel with the word line and is composed of a second metal interconnection layer electrically connected to the first source interconnection.

Abstract: According to this invention, in a non-volatile semiconductor memory device, each memory cell for storing 1-bit data consists of two transistors, one transistor constituting each memory cell is formed in a memory cell array consisting of a plurality of bit lines and a plurality of word lines, and the other transistor constituting each memory cell is formed in a second memory cell array consisting of a plurality of bit lines and a plurality of word lines.

Abstract: A data input circuit outputs input data in accordance with a write enable signal. A program control circuit generates different data items on the basis of the input data output from the data input circuit and the write enable signal, and turns programming transistors on/off in accordance with the different data items as generated. The programming transistors are connected to a pair of cell transistors forming an EPROM cells, and program into these cell transistors the different data items generated by the write control circuit. A timing circuit delays the timing at which the write enable signal is supplied to the write control circuit, until the input data is established within the data input circuit.

Abstract: A write control circuit is provided for supplying a gate of an n-channel enhancement-type writing transistor with a voltage corresponding to data when the data is written. The circuit comprises a reference potential-generation circuit, a differential amplifier, and a feedback circuit. The reference potential-generation circuit generates a reference potential substantially equal to the upper limit of that high level of each of the bit lines which is assumed at the time of writing. The differential amplifier has an input terminal to be supplied with the reference potential. A write voltage serving as an operation voltage is applied to the amplifier. The feedback circuit is connected between the other input terminal and output terminal of the differential amplifier.