Abstract: A differential cell-type non-volatile semiconductor device having first and second memory cell is disclosed. Two cell transistors of corresponding addresses in the first and second memory cell arrays are used to constitute a single memory cell. Each of writing transistors for writing data in the cell transistors is provided to the first and second memory cell arrays. Complementary data are written in the two cell transistors selected in the first and second memory cell arrays. Readout potentials from the two cell transistors are amplified by a differential amplifier, thereby reading out stored data. The memory device has a stress test control circuit for controlling, in a stress test mode, writing transistors such that they are all simultaneously turned on/off.

Abstract: An address detector of a redundancy memory cell is provided including a programming element for storing address data for replacing a defective cell with the redundancy cell. In a test mode, the redundancy cell may be written to regardless of whether or not a memory cell is defective. Thus, the redundancy cell may be tested without programming a programming element that replaces a defective cell with a redundancy cell. The detector further includes a latch for latching the state of the programming element, and a data setting element for setting the latch in a test mode.

Abstract: A nonvolatile semiconductor memory device comprising a power source terminal and a P-channel MOS transistor. A low power-source voltage is applied to the terminal during a read period. The source of the P-channel MOS transistor is coupled to the power source terminal. The conduction of the MOS transistor is controlled by data-writing operation. The drain of the MOS transistor is connected by a node to a plurality of bit lines. The device further comprises a plurality of memory cells and a plurality of N-channel MOS transistor. The memory cells have double-gate structure, each having a source coupled to the ground and a drain coupled to the corresponding bit line. Each N-channel MOS transistor has a source and a drain connected to the ground and the corresponding bit line, respectively, for discharging the bit line.

Abstract: An input protection circuit includes an input protection resistor and an input protection element. The input protection resistor is connected at one end to an input pad and connected at the other end to the gate of a MOS transistor provided at the input stage of an internal circuit. The input protection element is connected between the gate of the MOS transistor and at least one of a ground terminal and a power source. The input protection resistor includes a first impurity diffused region of a second conductivity type formed in the main surface area of a semiconductor substrate of a first conductivity type, and a second impurity diffused region of the second conductivity type which is formed in the first impurity diffused region to have an impurity concentration higher than the first impurity diffused region and have a diffusion depth smaller than the first impurity diffused region.

Abstract: A memory cell array includes data storing memory cells which are arranged in a matrix form of m rows.times.n columns. The data storing memory cells are selected by means of m word lines and n bit lines. Dummy capacitance cells are arranged on the (n+1)th column of the memory cell array, and are connected to the word lines. The dummy capacitance cells are each formed of a transistor which has the same construction as a field transistor having a gate electrode formed of a polysilicon layer or the data storing memory cell and whose source is set in the electrically floating condition. Array edge memory cells are arranged on the (m+1)th row of the memory cell array, and are connected to n bit lines. The array edge memory cells have no influence on the circuit operation. A dummy memory cell is arranged in an intersecting position of the (m+1)th row and the (n+1)th column.

Abstract: A semiconductor integrated circuit having a test mode in addition to a normal mode, includes a mode detecting circuit for detecting a state of each mode and generating a mode signal, a prebuffer circuit for receiving the mode signal generated by the mode detecting circuit, amplifying an input signal by using an output driving capacity corresponding to the mode signal, and outputting the amplified signal, and an output buffer circuit for receiving an output from the prebuffer circuit and outputting data outside the integrated circuit.

Abstract: An insulated gate type semiconductor device comprising an N channel transistor directly connected to an output terminal of the semiconductor device, the drain region of the N channel transistor comprising a region having a low-impurity concentration contiguous to the channel region, and the source region and a high-impurity concentration, comprising a region having a high-impurity concentration contiguous to the channel region, and an N channel transistor connected between the above mentioned N channel transistor and a low potential, the drain and source regions comprising regions having a high-impurity concentration contiguous to the channel region of the latter-recited N channel transistor.

Abstract: In a nonvolatile semiconductor memory, a plurality of nonvolatile semiconductor memory cells are arranged in a matrix form. Each of the memory cells is connected to a corresponding one of a plurality of bit lines and to a corresponding one of a plurality of word lines. The ends of the bit lines are commonly connected to a programming transistor for setting a programming mode through transistors for selecting the bit lines. The transistors are connected to column decoders and the word lines are connected to a row decoder. Furthermore, the other ends of the bit lines are connected to a common connecting line through transistors for setting a test mode and the common connecting line is connected to a node between the test mode transistors and a series circuit of a transistor and a dummy memory cell in a clamp circuit. The transistor of the clamp circuit is connected to a high voltage and the series circuit is connected to the ground.

Abstract: The first input terminal of a differential amplification type sense amplifier is connected to a first memory cell array and the second input terminal thereof is connected to a second memory cell array. Each of the first and second memory cell arrays is formed of a plurality of memory cells arranged in a matrix form. Each of the memory cells in the first memory cell array and a corresponding one of the memory cells in the second memory cell array are provided in the form of pair for each bit. Complementary data is programmed into the paired memory cells according to programming data. In the data readout operation, the potential of data read out from the paired memory cells is amplified by means of the differential amplification type sense amplifier. First and second loads are connected to the first and second input terminals of the differential amplification type sense amplifier.

Abstract: This invention provides a non-volatile semiconductor memory having a first node and a second node, the second node having a ground potential. The invention includes a plurality of non-volatile memory cells each having a drain and a threshold potential, the cells, for storing data written into the cells at a predetermined normal writing voltage. A plurality of bit lines, each memory cell being connected to one of the bit lines, transfer data to and from the memory cells. A circuit connected to the bit lines simultaneously tests the memory cells of all the bit lines at the normal writing voltage to detect changes in the threshold potential.

Abstract: A nonvolatile semiconductor memory according to this invention is so constructed that different data readout references are used in an ordinary readout mode and in a program verification mode. The different read-out references can be set by changing reference input potential VREF supplied to a differential sense amplifier for amplifying a potential derived onto a bit line from a memory cell, or by changing an input threshold level of a circuit for sensing the potential on the bit line. In this case, the readout reference in the program verification mode is set severe, or high, in comparison with that in the ordinary readout mode.

Abstract: A nonvolatile semiconductor memory of this invention is constituted to latch input data into data latch circuits and at the same time control the programming operation of the bit line load transistors when the chip enable signal is made active and a page programming power source voltage is set at the programming voltage, while the output enable signal is kept inactive. Further, when the output enable signal is made active or the programming power source voltage is set at a voltage different from the programming voltage, the data latch circuits are reset. The data latch circuits can be selectively specified by a preset combination of bits.

Abstract: A voltage level converting circuit for outputting an output signal of a write voltage level responsive to a read voltage level input signal comprises an inverter circuit biased with a power supply of the first voltage level. The input signal is supplied through a transfer gate circuit. A MOS transistor is provided between the input of the inverter circuit and a power supply of the write voltage level to pull-up the voltage level of the input to the inverter circuit responsive to the output of the inverter circuit. Another MOS transistor is provided between the output of the inverter circuit and ground to pull-down the output voltage level responsive to the input signal.

Abstract: A bipolar transistor for clamping an excess input potential is provided near an input pad. A signal from the input pad is supplied through a wire to the gate of a MOS transistor in the input stage. A diode is provided near the gate of the MOS transistor. The diode absorbs a potential oscillation generated in the wire near the gate of the transistor, which is due to action of an inductance involved in the wire.

Abstract: A semiconductor memory device of the invention has a plurality of floating gate memory cells. A detector detects the data stored in a floating gate memory cell selected by a decoder and produces a corresponding detection signal. A load circuit amplifies the detection signal. The amplified detection signal is supplied to a differential amplifier. The differential amplifier compares the voltage of the amplified detection signal with a reference voltage from a reference voltage generator and produces a binary signal corresponding to the storage contents in the floating gate memory. The load circuit is a p-channel enhancement-type MOS transistor. The load transistor has a gate and drain which are connected to the node between the detector and the differential amplifier, and also has a source and substrate which receive a predetermined voltage.

Abstract: A second impurity diffusion layer is formed in a semiconductor substrate at a fixed distance from a first diffusion layer in the substrate. The diffusion layer is supplied with a program potential. An electrode is placed on the channel region between the first and second diffusion layers. Non-selected memory cells are prevented from becoming half-selected by electrically separating the first diffusion layer from the program potential according to signals from the electrode, resulting in substantial improvements in the reliability of the semiconductor device.

Abstract: A nonvolatile semiconductor memory of this invention is obtained by dividing a memory cell array in which EPROM cells are provided in a matrix form and a write circuit into a plurality of blocks, commonly connecting sources of cell transistors in each block of the memory cell array, and connecting the common source of each block to a ground node through a corresponding resistive component.

Abstract: A nonvolatile semiconductor memory device includes a power voltage select circuit that is comprised of first and second power source nodes, an output node, first and second depletion type MOS transistors connected in series between the first power source node and the output node, a third MOS transistor connected between an interconnection point between the first and second depletion type MOS transistors and the second power source node, and a fourth MOS transistor connected between the second power source node and the output node.

Abstract: A differential amplifier having input terminals connected to first and second nodes lying between the main nonvolatile memory cell section and the nonvolatile dummy cell circuit is used as a sense amplifier. The first and second nodes are pre-charged to a high potential level prior to the data readout operation. The memory cell section and the dummy cell circuit are set in the capacitively balanced condition, thereby making it possible to correctly read out data at a high speed.

Abstract: A nonvolatile semiconductor memory device comprising a matrix array of memory cells, word lines for driving the rows of memory cells, bit lines for reading data from columns of memory cells, a plurality of first MOS transistors provided for these bit lines, respectively, a second MOS transistor having a source coupled to the bit lines by the first MOS transistors, a drain coupled to a VCC terminal, and a gate connected to receive a predetermined bias voltage, a row decoder for selecting one of the word lines in accordance with a row-address signal, and a column decoder for turning on one of the first MOS transistors in accordance with a column-address signal.