Abstract: A semiconductor memory device includes a main memory cell array, a redundancy memory cell array, bonding pads for receiving an address signal, a row decoder for selecting a row of the main memory cell array in accordance with the row address signal, and an exchange controller connected to receive the address signal, which is programmable to inhibit the selective operation of the row decoder to select the row of the redundancy memory cell array, in response to specific address signals. The semiconductor memory device further includes bonding pads, each for receiving a test signal. The exchange controller is connected to receive the test signal for inhibiting the selective operation of the row decoder and selecting the row of the redundancy memory cell array, in response to the test signal.

Abstract: A nonvolatile semiconductor memory device is disclosed comprising a bit line connected to the drain of a memory cell transistor forming a nonvolatile memory cell, a first p-channel MOS transistor, the drain and gate of the first transistor being connected to a node, and the source of the first transistor being connected to a power source potential, second and third n-channel MOS transistors connected in series between the node and a reference potential, the drain and gate of the second transistor being interconnected, and the drain and gate of the third transistor being interconnected, and a fourth n-channel MOS transistor for controlling charging of the bit line, one terminal of the drain-source path of the fourth transistor being connected to the power source potential and the other terminal being connected to the bit line, and the gate of the fourth transistor being connected to the node.

Abstract: Disclosed is a nonvolatile semiconductor memory having a high access speed and high reliability. The memory includes a source diffusion region extending in one direction, a pair of first word lines arranged in parallel with the source diffusion region, such that the source diffusion region is interposed therebetween, drain diffusion regions disposed to face the source diffusion region, with the first word lines interposed therebetween, bit lines electrically connected to the drain diffusion regions and arranged to cross the first word lines, a channel region formed below each of the first word lines and positioned between the source diffusion region and the drain diffusion region, a floating gate electrode formed in an electrically floating manner above the channel region and below one of the pair of the first word lines, and a second word line formed above the source region and positioned between and electrically connected to the pair of first word lines.

Abstract: Each memory cell in an EPROM includes two memory cell transistors which share a common floating gate and have two separated drains, one of which is connected to a read bit line and the other of which is connected to write bit line. In this EPROM, the read memory cell transistor of the read bit line has a lower hot electron injection rate than the hot electron injection rate of the write memory cell transistor of the write bit line. A bit line voltage booster is connected to the read bit line.

Abstract: There is disclosed a semiconductor memory device comprising a memory cell connected to a bit line, and a clamp circuit comprising a load MOS transistor connected between a power source voltage and the bit line, for clamping the power source voltage and applying the clamped voltage to the bit line. The semiconductor memory device further comprises a bypass circuit connected between the bit line and a reference voltage, for bypassing from the bit line to the reference voltage an electric current the amount of which is substantially equal to that of a weak inversion current of the load MOS transistor flowing into said bit line.

Abstract: A semiconductor memory device in which the differential amplifier circuit compares a potential of a bit line to which memory cells storing information are connected with a reference potential of a dummy line to which a dummy cell is connected, and detects information stored in each of the memory cells. The semiconductor memory device comprises a circuit which discharges both the bit line and the dummy line to a low potential when the chip enable inverted signal is supplied. When the chip enable signal is supplied, therefore, the differential amplifier circuit can detect a difference between the bit line potential and the dummy line potential before the bit line is fully charged up. This makes it possible to produce the chip enable access time and to realize higher speed operations.

Abstract: A voltage converter circuit has an input terminal for receiving an input binary signal and a gate for generating an output binary signal corresponding to the input binary signal. An output signal from the gate is supplied to a first input terminal of an inverter through a transistor and further to a second input terminal of the inverter directly, so as to immediately stabilize the output signal from the voltage converter circuit. The inverter inverts the input signal to a higher-voltage binary signal. When a voltage level of the higher-voltage binary signal reaches a given voltage level while the voltage level of the higher-voltage binary signal changes, a feedback circuit is operated to set the input signal supplied to the first input terminal of the inverter at a higher voltage.