Patents by Inventor Shigeru Matake

Shigeru Matake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8355204
    Abstract: The present invention provides a highly efficient light-extraction layer and an organic electroluminescence element excellent in light-extraction efficiency. The light-extraction layer of the present invention comprises a reflecting layer and a three-dimensional diffraction layer formed thereon. The diffraction layer comprises fine particles having a variation coefficient of the particle diameter of 10% or less and of a matrix having a refractive index different from that of the fine particles. The particles have a volume fraction of 50% or more based on the volume of the diffraction layer. The particles are arranged to form first areas having short-distance periodicity, and the first areas are disposed and adjacent to each other in random directions to form second areas. The organic electroluminescence element of the present invention comprises the above light-extraction layer.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: January 15, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu Nakanishi, Akira Fujimoto, Shigeru Matake, Koji Asakawa
  • Publication number: 20100183866
    Abstract: The present invention provides a method for easily producing a particle-arranged structure. In the structure produced by the method, particles are regularly arranged. The method of the present invention comprises: preparing a dispersion comprising a solvent, a polymerizable compound dissolved in the solvent and particles insoluble and dispersed uniformly in the solvent; spin-coating the dispersion on a substrate so as to arrange the particles in the liquid phase of the dispersion; and then curing the polymerizable compound.
    Type: Application
    Filed: January 14, 2010
    Publication date: July 22, 2010
    Inventors: Akira FUJIMOTO, Tsutomu Nakanishi, Shigeru Matake, Koji Asakawa
  • Publication number: 20090224660
    Abstract: The present invention provides a highly efficient light-extraction layer and an organic electroluminescence element excellent in light-extraction efficiency. The light-extraction layer of the present invention comprises a reflecting layer and a three-dimensional diffraction layer formed thereon. The diffraction layer comprises fine particles having a variation coefficient of the particle diameter of 10% or less and of a matrix having a refractive index different from that of the fine particles. The particles have a volume fraction of 50% or more based on the volume of the diffraction layer. The particles are arranged to form first areas having short-distance periodicity, and the first areas are disposed and adjacent to each other in random directions to form second areas. The organic electroluminescence element of the present invention comprises the above light-extraction layer.
    Type: Application
    Filed: December 31, 2008
    Publication date: September 10, 2009
    Inventors: Tsutomu Nakanishi, Akira Fujimoto, Shigeru Matake, Koji Asakawa
  • Patent number: 7414417
    Abstract: According to one aspect of the invention, a contact sheet for testing electronic parts, comprising an insulating porous layer; and a connection electrode which is disposed on the insulating porous layer and electrically connect the electrode or terminal of the electronic parts and the terminal of a test apparatus; wherein the connection electrode is embedded below at least one main surface of the insulating porous layer.
    Type: Grant
    Filed: July 8, 2004
    Date of Patent: August 19, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoko Yamaguchi, Hideo Aoki, Chiaki Takubo, Toshiro Hiraoka, Yasuyuki Hotta, Shigeru Matake
  • Patent number: 7370412
    Abstract: An electronic device connecting method according to a first aspect of the present invention includes: mounting an electronic device having at least one electrode portion on a sheet-like porous member having a hole therein so that the electrode portion is close to the porous member; selectively irradiating a predetermined region of the porous member, on which the electronic device is mounted, with energy lines to form a latent image in an irradiated or non-irradiated portion of the porous member, the predetermined region including a portion close to the electrode portion; after irradiating with the energy lines, filling a conductive material in a hole of the latent image of the porous member to form a conductive portion; and bonding and integrating the porous member, in which the conductive portion is formed, to and with the electronic device.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: May 13, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiro Hiraoka, Mitsuyoshi Endo, Naoko Yamaguchi, Yasuyuki Hotta, Shigeru Matake, Hideo Aoki, Misa Sawanobori
  • Patent number: 7329458
    Abstract: Disclosed is a wiring member comprising a sheet-like porous substrate provided with a large number of open-cells which are three-dimensionally branched and opened to a first major surface as well as to a second major surface of the porous substrate, and a conductive portion formed on the first major surface of the porous substrate and formed at least partially an inter-penetrating structure together with the porous substrate at an interface of the porous substrate. The apertures of the open-cells on the first major surface have an average diameter and an average number of the apertures, at least one of which is smaller than that of the second major surface.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: February 12, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiro Hiraoka, Yasuyuki Hotta, Shigeru Matake, Misa Sawanobori, Kou Yamada
  • Patent number: 7312621
    Abstract: A semiconductor test unit comprises a test circuit for inputting/outputting a test signal to/from an examined electronic product, a test signal wiring electrically connected to the test circuit, a contact board electrically connected to an electrode of the examined electronic product and provided with an electrically conductive via to which the test signal is transmitted, a multilayer circuit board electrically connected to the conductive via and the test signal wiring, located under the bottom face of the contact board, and provided with at least one through-hole, and a vacuum attachment mechanism for attaching thereto and holding the examined electronic product, the contact board, and the multilayer circuit board by vacuum. The contact board is made of an insulative material, has top and bottom faces, and is provided with at least one through-hole.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: December 25, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoko Yamaguchi, Yoshiaki Sugizaki, Hideo Aoki, Toshiro Hiraoka, Yasuyuki Hotta, Shigeru Matake, Misa Sawanobori
  • Patent number: 6906423
    Abstract: A mask used for exposing a porous substrate to form a first region and a second region, the first region being filled with a conductive material piercing through the entire thickness of the porous substrate to constitute an interfacial conductive portion, the second region being filled with a conductive material not piercing the entire thickness of the porous substrate to constitute a non-interfacial conductive portion. The mask includes a first light-transmitting region for exposing the first region, and a second light-transmitting region for exposing the second region, said second light-transmitting region including an aggregation of fine patterns of which an average aperture ratio is not more than 50% of an average aperture ratio of the first light-transmitting region and a size of said fine patterns of the second light-transmitting region being in the range of 0.1 ?m to 10 ?m.
    Type: Grant
    Filed: September 26, 2003
    Date of Patent: June 14, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Asakawa, Yasuyuki Hotta, Shigeru Matake, Toshiro Hiraoka
  • Patent number: 6899999
    Abstract: Disclosed is a method of manufacturing a composite member having a conductive pattern, comprising (1) forming on a surface of an insulating body a photosensitive layer containing both a photosensitive compound forming an ion-exchange group upon irradiation with an energy beam and a crosslinkable compound having a crosslinkable group, (2) forming a pattern of ion-exchange groups by selectively exposing the photosensitive layer to an energy beam so as to form an ion-exchange group in the exposed portion, (3) crosslinking the crosslinkable compound contained in at least the exposed portion of the photosensitive layer, (4) allowing metal ions, or a metal colloid to be adsorbed on the pattern of ion-exchange groups formed by the selectively exposing, and (5) forming a composite member having conductive pattern by depositing a conductive material on the pattern of ion-exchange groups having the metal ions, or the metal colloid adsorbed thereon using an electroless plating.
    Type: Grant
    Filed: March 7, 2002
    Date of Patent: May 31, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiro Hiraoka, Koji Asakawa, Yasuyuki Hotta, Shigeru Matake
  • Publication number: 20050024067
    Abstract: According to one aspect of the invention, a contact sheet for testing electronic parts, comprising an insulating porous layer; and a connection electrode which is disposed on the insulating porous layer and electrically connect the electrode or terminal of the electronic parts and the terminal of a test apparatus; wherein the connection electrode is embedded below at least one main surface of the insulating porous layer.
    Type: Application
    Filed: July 8, 2004
    Publication date: February 3, 2005
    Inventors: Naoko Yamaguchi, Hideo Aoki, Chiaki Takubo, Toshiro Hiraoka, Yasuyuki Hotta, Shigeru Matake
  • Patent number: 6835889
    Abstract: The present invention provides a composite material such as a passive element, a passive element composite component, a substrate with a built-in passive element and a composite wiring substrate which are free from, for example, a layer peeling problem and enables high density packaging with ease. In the present invention, a porous base material is divided into plural functional regions and a material having different electromagnetic characteristics is filled in a pore of the porous base material of each functional region, to form a passive element or a wiring substrate. Among the aforementioned plural functional regions, at least one functional region is a conductive material region filled with a conductive material and other regions are filled with a high-dielectric material, a high-permeability material or a low-dielectric material.
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: December 28, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiro Hiraoka, Yasuyuki Hotta, Koji Asakawa, Shigeru Matake
  • Publication number: 20040205402
    Abstract: A semiconductor test unit comprises a test circuit for inputting/outputting a test signal to/from an examined electronic product, a test signal wiring electrically connected to the test circuit, a contact board electrically connected to an electrode of the examined electronic product and provided with an electrically conductive via to which the test signal is transmitted, a multilayer circuit board electrically connected to the conductive via and the test signal wiring, located under the bottom face of the contact board, and provided with at least one through-hole, and a vacuum attachment mechanism for attaching thereto and holding the examined electronic product, the contact board, and the multilayer circuit board by vacuum. The contact board is made of an insulative material, has top and bottom faces, and is provided with at least one through-hole.
    Type: Application
    Filed: March 31, 2003
    Publication date: October 14, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Naoko Yamaguchi, Yoshiaki Sugizaki, Hideo Aoki, Toshiro Hiraoka, Yasuyuki Hotta, Shigeru Matake, Misa Sawanobori
  • Publication number: 20040191497
    Abstract: Disclosed is a wiring member comprising a sheet-like porous substrate provided with a large number of open-cells which are three-dimensionally branched and opened to a first major surface as well as to a second major surface of the porous substrate, and a conductive portion formed on the first major surface of the porous substrate and formed at least partially an inter-penetrating structure together with the porous substrate at an interface of the porous substrate. The apertures of the open-cells on the first major surface have an average diameter and an average number of the apertures, at least one of which is smaller than that of the second major surface.
    Type: Application
    Filed: October 29, 2003
    Publication date: September 30, 2004
    Inventors: Toshiro Hiraoka, Yasuyuki Hotta, Shigeru Matake, Misa Sawanobori, Kou Yamada
  • Patent number: 6709806
    Abstract: Disclosed is a method of manufacturing a composite member in which a conductive portion is selectively formed in an insulator. The method comprises the steps of forming a photosensitive composition layer containing a compound forming an ion-exchange group upon irradiation with light having a wavelength not shorter than 280 nm within or on the surface of an insulator, exposing selectively the photosensitive composition layer to light having a wavelength not shorter than 280 nm, forming an ion-exchange group in the exposed portion, and bonding a metal or metal ions to the ion-exchange group formed in the exposed portion of the photosensitive composition layer.
    Type: Grant
    Filed: March 15, 2001
    Date of Patent: March 23, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuyuki Hotta, Toshiro Hiraoka, Koji Asakawa, Shigeru Matake
  • Publication number: 20040009683
    Abstract: An electronic device connecting method according to a first aspect of the present invention includes: mounting an electronic device having at least one electrode portion on a sheet-like porous member having a hole therein so that the electrode portion is close to the porous member; selectively irradiating a predetermined region of the porous member, on which the electronic device is mounted, with energy lines to form a latent image in an irradiated or non-irradiated portion of the porous member, the predetermined region including a portion close to the electrode portion; after irradiating with the energy lines, filling a conductive material in a hole of the latent image of the porous member to form a conductive portion; and bonding and integrating the porous member, in which the conductive portion is formed, to and with the electronic device.
    Type: Application
    Filed: July 3, 2003
    Publication date: January 15, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toshiro Hiraoka, Mitsuyoshi Endo, Naoko Yamaguchi, Yasuyuki Hotta, Shigeru Matake, Hideo Aoki, Misa Sawanobori
  • Patent number: 6649516
    Abstract: Disclosed is a method for manufacturing a composite member comprising a porous substrate, a via, and a wiring. The method comprises exposing a first region and a second region in the porous substrate to a exposure beam through a mask, the second region exposed by the exposure beam not more than 50% of the exposure of the first region, the exposure beam having the wavelength that an average size of voids of the porous substrate is, as expressed by a radius of gyration, {fraction (1/20)} to 10 times, and forming the via and the wiring by infiltrating a conductive material into the first region and the second region respectively.
    Type: Grant
    Filed: June 5, 2002
    Date of Patent: November 18, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Asakawa, Yasuyuki Hotta, Shigeru Matake, Toshiro Hiraoka
  • Publication number: 20030107465
    Abstract: The present invention provides a composite material such as a passive element, a passive element composite component, a substrate with a built-in passive element and a composite wiring substrate which are free from, for example, a layer peeling problem and enables high density packaging with ease. In the present invention, a porous base material is divided into plural functional regions and a material having different electromagnetic characteristics is filled in a pore of the porous base material of each functional region, to form a passive element or a wiring substrate. Among the aforementioned plural functional regions, at least one functional region is a conductive material region filled with a conductive material and other regions are filled with a high-dielectric material, a high-permeability material or a low-dielectric material.
    Type: Application
    Filed: September 23, 2002
    Publication date: June 12, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toshiro Hiraoka, Yasuyuki Hotta, Koji Asakawa, Shigeru Matake
  • Publication number: 20030022102
    Abstract: Disclosed is a method of manufacturing a composite member having a conductive pattern, comprising (1) forming on a surface of an insulating body a photosensitive layer containing both a photosensitive compound forming an ion-exchange group upon irradiation with an energy beam and a crosslinkable compound having a crosslinkable group, (2) forming a pattern of ion-exchange groups by selectively exposing the photosensitive layer to an energy beam so as to form an ion-exchange group in the exposed portion, (3) crosslinking the crosslinkable compound contained in at least the exposed portion of the photosensitive layer, (4) allowing metal ions, or a metal colloid to be adsorbed on the pattern of ion-exchange groups formed by the selectively exposing, and (5) forming a composite member having conductive pattern by depositing a conductive material on the pattern of ion-exchange groups having the metal ions, or the metal colloid adsorbed thereon using an electroless plating.
    Type: Application
    Filed: March 7, 2002
    Publication date: January 30, 2003
    Inventors: Toshiro Hiraoka, Koji Asakawa, Yasuyuki Hotta, Shigeru Matake
  • Publication number: 20020197834
    Abstract: Disclosed is a method for manufacturing a composite member comprising a porous substrate, a via, and a wiring. The method comprises exposing a first region and a second region in the porous substrate to a exposure beam through a mask, the second region exposed by the exposure beam not more than 50% of the exposure of the first region, the exposure beam having the wavelength that an average size of voids of the porous substrate is, as expressed by a radius of gyration, {fraction (1/20)} to 10 times, and forming the via and the wiring by infiltrating a conductive material into the first region and the second region respectively.
    Type: Application
    Filed: June 5, 2002
    Publication date: December 26, 2002
    Inventors: Koji Asakawa, Yasuyuki Hotta, Shigeru Matake, Toshiro Hiraoka
  • Publication number: 20020004180
    Abstract: Disclosed is a method of manufacturing a composite member in which a conductive portion is selectively formed in an insulator. The method comprises the steps of forming a photosensitive composition layer containing a compound forming an ion-exchange group upon irradiation with light having a wavelength not shorter than 280 nm within or on the surface of an insulator, exposing selectively the photosensitive composition layer to light having a wavelength not shorter than 280 nm, forming an ion-exchange group in the exposed portion, and bonding a metal or metal ions to the ion-exchange group formed in the exposed portion of the photosensitive composition layer.
    Type: Application
    Filed: March 15, 2001
    Publication date: January 10, 2002
    Inventors: Yasuyuki Hotta, Toshiro Hiraoka, Koji Asakawa, Shigeru Matake