Patents by Inventor Shigeru Nakagawa

Shigeru Nakagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6714573
    Abstract: A vertical cavity surface emitting laser (VCSEL) includes a semiconductor device having a pair of mirror portions, an active region, a tunnel junction, a pair of cladding layers and a substrate. Heat generated by the VCSEL dissipates through the cladding layers, which utilize an indium phosphide material. The VCSEL also includes selective etches that are used to aperture the active region to allow electric current to be injected into the active region.
    Type: Grant
    Filed: August 21, 2001
    Date of Patent: March 30, 2004
    Assignee: The Regents of the University of California
    Inventors: Larry A. Coldren, Eric M. Hall, Shigeru Nakagawa
  • Patent number: 6687281
    Abstract: A vertical cavity surface emitting laser (VCSEL) includes a semiconductor device having a pair of mirror portions, an active region, a tunnel junction, a pair of cladding layers and a substrate. Heat generated by the VCSEL dissipates through the cladding layers, which utilize an indium phosphide material. The VCSEL also includes selective etches that are used to aperture the active region to allow electric current to be injected into the active region.
    Type: Grant
    Filed: August 21, 2001
    Date of Patent: February 3, 2004
    Assignee: The Regents of the University of California
    Inventors: Larry A. Coldren, Eric M. Hall, Shigeru Nakagawa
  • Patent number: 6486984
    Abstract: A method and a system for monitoring specific channels in a WDM system involve splitting a WDM signal into multiple parallel signals, filtering the parallel signals with corresponding individually tunable filters in order to pass specific channels to each filter, and then detecting the presence of passed channels with dedicated detectors that correspond to the tunable filters. In a preferred embodiment, the initial WDM signal is demultiplexed by wavelength into multiple different transmission groups and each filter can be individually tuned over a channel range that corresponds to the range of channels within the transmission group that is directed to the filter. The preferred individually tunable filters are vertical cavity filters formed utilizing semiconductor wafer processing techniques, and the preferred photodetectors are simple low cost single-cell photodetectors.
    Type: Grant
    Filed: June 7, 1999
    Date of Patent: November 26, 2002
    Assignee: Agilent Technologies, Inc.
    Inventors: Douglas M. Baney, Norihide Yamada, Satoshi Watanabe, Shigeru Nakagawa, Yoshikatsu Ichimura
  • Publication number: 20020150130
    Abstract: A tunable VCSEL assembly comprises a first substrate upon which a first epitaxial structure is formed, the first epitaxial structure having areas of different optical properties comprising a front mirror or reflector, an active region, a cavity and a rear surface. A back subassembly comprises a second substrate upon which a second epitaxial structure is formed, the second epitaxial structure having areas of different optical properties and comprising a back movable mirror or reflector having a forward surface. Bonding elements or materials are emplaced at selected spaced apart corresponding areas on each of the front subassembly and the back subassembly such that upon engagement, the front subassembly and the back subassembly are permanently bonded to one another. The front subassembly and the back subassembly are configured such that there is an elastic optically transparent gap between the front surface of the back movable mirror of the back subassembly and the rear surface of the front subassembly.
    Type: Application
    Filed: April 16, 2001
    Publication date: October 17, 2002
    Inventors: Larry A. Coldren, Eric Michael Hall, Shigeru Nakagawa
  • Publication number: 20020150129
    Abstract: A tunable VCSEL assembly comprises a first substrate upon which a first epitaxial structure is formed, the first epitaxial structure having areas of different optical properties comprising a front mirror or reflector, an active region, a cavity and a rear surface. A back subassembly comprises a second substrate upon which a second epitaxial structure is formed, the second epitaxial structure having areas of different optical properties and comprising a back movable mirror or reflector having a forward surface. Bonding elements or materials are emplaced at selected spaced apart corresponding areas on each of the front subassembly and the back subassembly such that upon engagement, the front subassembly and the back subassembly are permanently bonded to one another. The front subassembly and the back subassembly are configured such that there is an elastic optically transparent gap between the front surface of the back movable mirror of the back subassembly and the rear surface of the front subassembly.
    Type: Application
    Filed: April 16, 2001
    Publication date: October 17, 2002
    Inventors: Larry A. Coldren, Eric Michael Hall, Shigeru Nakagawa
  • Publication number: 20020128882
    Abstract: This system comprises a usage status detection means for detecting the usage status of a vehicle, data input means for inputting data relating to the maintenance or management of a vehicle, and insurance premium calculation means for calculating vehicle insurance premiums based on detection results and inputted data.
    Type: Application
    Filed: February 27, 2002
    Publication date: September 12, 2002
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Shigeru Nakagawa, Kenji Mori, Akira Shinada, Katsuhiko Nunokawa, Hiroaki Okajima, Makoto Sasaki
  • Publication number: 20020101894
    Abstract: A method for aperturing a vertical-cavity surface-emitting laser (VCSEL), for increasing the external quantum efficiency and decreasing the threshold current, involves an etching mixture that is applied to the active region of the VCSEL. The etching mixture is designed in a manner to selectively etch the active region of the VCSEL at a rate substantially faster than the etch rate of at least one of the multiple DBRS associated with the VCSEL.
    Type: Application
    Filed: August 21, 2001
    Publication date: August 1, 2002
    Inventors: Larry A. Coldren, Eric M. Hall, Shigeru Nakagawa, Guilhem Almuneau
  • Publication number: 20020090016
    Abstract: A vertical cavity surface emitting laser (VCSEL) includes a semiconductor device having a pair of mirror portions, an active region, a tunnel junction, a pair of cladding layers and a substrate. Heat generated by the VCSEL dissipates through the cladding layers, which utilize an indium phosphide material. The VCSEL also includes selective etches that are used to aperture the active region to allow electric current to be injected into the active region.
    Type: Application
    Filed: August 21, 2001
    Publication date: July 11, 2002
    Inventors: Larry A. Coldren, Eric M. Hall, Shigeru Nakagawa
  • Publication number: 20020075926
    Abstract: A vertical cavity surface emitting laser (VCSEL) includes a semiconductor device having a pair of mirror portions, an active region, a tunnel junction, a pair of cladding layers and a substrate. Heat generated by the VCSEL dissipates through the cladding layers, which utilize an indium phosphide material. The VCSEL also includes selective etches that are used to aperture the active region to allow electric current to be injected into the active region.
    Type: Application
    Filed: August 21, 2001
    Publication date: June 20, 2002
    Inventors: Larry A. Coldren, Eric M. Hall, Jin K. Kim, Shigeru Nakagawa
  • Publication number: 20020071464
    Abstract: A vertical cavity surface emitting laser (VCSEL) includes a semiconductor device having a pair of mirror portions, an active region, a tunnel junction, a pair of cladding layers and a substrate. Heat generated by the VCSEL dissipates through the cladding layers, which utilize an indium phosphide material. The VCSEL also includes selective etches that are used to aperture the active region to allow electric current to be injected into the active region.
    Type: Application
    Filed: August 21, 2001
    Publication date: June 13, 2002
    Inventors: Larry A. Coldren, Eric M. Hall, Shigeru Nakagawa
  • Patent number: 6375255
    Abstract: A rear passenger seat adapted for use in a vehicle compartment, the passenger seat having a seat cushion the front end portion of which is supported by a support leg assembly pivotally mounted on a recessed portion of the compartment floor and the rear end portion of which is locked in place by means of a lock mechanism on a deck portion of the compartment floor, wherein the support leg assembly includes a support leg pivotally mounted on the recessed portion of the compartment floor for pivotal movement in a fore-and-aft direction, a leg support member pivoted at its lower end to an upper end of the support leg and pivoted at its upper end to a support frame of the seat cushion to be folded forward at the upper end of the support leg and retainer means provided on a vertical wall between the recessed portion and deck portion of the compartment floor for releasably retaining the support leg assembly in an upright position by engagement therewith, and wherein a pneumatic spring is disposed a between the leg su
    Type: Grant
    Filed: August 10, 2000
    Date of Patent: April 23, 2002
    Assignees: Toyota Jidosha Kabushiki Kaisha, Araco Kabushiki Kaisha, Kanto Jidosha Kogyo Kabushiki Kaisha
    Inventors: Tsutomu Maruta, Naoki Wakasugi, Shigeru Nakagawa
  • Publication number: 20010015442
    Abstract: A light emitting device is constructed on a substrate. The device includes an n-type semiconductor layer in contact with the substrate, an active layer for generating light, the active layer being in electrical contact with the n-type semiconductor layer. A p-type semiconductor layer is in electrical contact with the active layer, and a p-electrode is in electrical contact with the p-type semiconductor layer. The p-electrode includes a layer of silver in contact with the p-type semiconductor layer. A bonding layer is formed overlying the silver layer to make an electrical connection to the silver layer. The silver layer may be thin and transparent or thicker (greater than 20 nm) and reflective.
    Type: Application
    Filed: January 16, 2001
    Publication date: August 23, 2001
    Inventors: You Kondoh, Satoshi Watanabe, Yawara Kaneko, Shigeru Nakagawa, Norihide Yamada
  • Patent number: 6239490
    Abstract: A p-contact that comprises a contact layer of a p-type Group III-nitride semiconductor having an exposed surface and an electrode layer of palladium (Pd) located on the exposed surface of the contact layer. The p-contact is made by providing a p-type Group III-nitride semiconductor contact layer having an exposed surface, and depositing an electrode layer of palladium on the exposed surface of the contact layer. Preferably, the p-contact is annealed for a prolonged annealing time after the electrode layer is deposited, and the exposed surface of the contact layer is etched using hydrofluoric acid (HF) before depositing the electrode layer.
    Type: Grant
    Filed: February 9, 1998
    Date of Patent: May 29, 2001
    Assignee: Agilent Technologies, Inc.
    Inventors: Norihide Yamada, Shigeru Nakagawa, Yoshifumi Yamaoka, Tetsuya Takeuchi, Yawara Kaneki
  • Patent number: 6194743
    Abstract: A light emitting device constructed on a substrate. The device includes an n-type semiconductor layer in contact with the substrate, an active layer for generating light, the active layer being in electrical contact with the n-type semiconductor layer. A p-type semiconductor layer is in electrical contact with the active layer, and a p-electrode is in electrical contact with the p-type semiconductor layer. The p-electrode includes a layer of silver in contact with the p-type semiconductor layer. In the preferred embodiment of the present invention, the n-type semiconductor layer and the p-type semiconductor layer are constructed from group III nitride semiconductor materials. In one embodiment of the invention, the silver layer is sufficiently thin to be transparent. In other embodiments, the silver layer is thick enough to reflect most of the light incident thereon. A fixation layer is preferably provided over the silver layer.
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: February 27, 2001
    Assignee: Agilent Technologies, Inc.
    Inventors: You Kondoh, Satoshi Watanabe, Yawara Kaneko, Shigeru Nakagawa, Norihide Yamada
  • Patent number: 5729567
    Abstract: First and second layers are alternately laminated on the semiconductor substrate, providing a multilayer structure in which the resultant residual stress in the layered structure is significantly decreased. One embodiment of the invention is applied to a vertical cavity surface emitting laser having a dielectric multilayer mirror comprised of pairs of a first layer (SiO.sub.2 layer) and a second layer (TiO.sub.2 layer). Each layer has a prescribed thickness and is formed by deposition on a semiconductor (GaAs) substrate. When the layers are deposited on the semiconductor substrate, the first layer is preferably formed to exhibit a residual compressive stress, while the second layer is preferably formed to exhibit a residual tensile stress having a magnitude that is equal to or almost equal to the residual compressive stress of the first layer.
    Type: Grant
    Filed: April 25, 1996
    Date of Patent: March 17, 1998
    Assignee: Hewlett-Packard Company
    Inventor: Shigeru Nakagawa
  • Patent number: 5530381
    Abstract: To provide a type of logic circuit, characterized by the fact that the novel-configuration logic circuit can be easily manufactured in a bipolar process, having a high integration degree and allowing a high-speed operation. For standard longitudinal-type NPN transistor TR0, its emitter E0 is connected to bias terminal BIAS, base B0 is connected to voltage source +Vcc, and collector C0 is connected to base B1 of PNP transistor TR1. For lateral-type PNP transistor TR1, emitter E1 is connected to voltage source Vxx, base B1 is connected to both the collector Co of NPN transistor TR0 and input terminal IN, and collectors C1, C2, C3, . . . Cn are connected to output terminals OUT1, OUT2, PUT3, . . . OUTn, respectively. Schottky diodes SBD1, SBD2, SBD3, . . . SBDn are connected between base B1 and collectors C1, C2, C3, . . . Cn of NPN transistor TR1 with a cathode on the side of the base and with an anode on the side of the collector.
    Type: Grant
    Filed: December 20, 1994
    Date of Patent: June 25, 1996
    Assignee: Texas Instruments Incorporated
    Inventor: Shigeru Nakagawa
  • Patent number: 5497118
    Abstract: The invention is intended to offer a signal selector circuit and a signal-generating circuit which are excellent in linearity between input and output signals at high frequencies and in isolation between input signals and isolation between output signals and which do not produce distortion. When an output signal is taken from OUT.sub.1, a circuit connected with the gate terminal of Q.sub.11 is made to have a high impedance, and a cutoff voltage deeper than the pinchoff voltage is applied to the gate of Q.sub.12. With respect to each of Q.sub.11, Q.sub.12, the gate is connected with the source by R.sub.11 or R.sub.12. Both Q.sub.11 and Q.sub.12 have depletion characteristics. The resistances of R.sub.11 and R.sub.12 are lower than the impedances of Q.sub.15 and Q.sub.16 when they drive the gates so as to turn on Q.sub.11 and Q.sub.12. In this case, therefore, the voltage between the gate and the source of Q.sub.11 is made null and Q.sub.11 conducts. Q.sub.12 is cut off.
    Type: Grant
    Filed: July 19, 1993
    Date of Patent: March 5, 1996
    Assignee: Hewlett-Packard Company
    Inventors: Toshiaki Ueno, Shigeru Nakagawa
  • Patent number: 5402016
    Abstract: To provide a type of logic circuit, characterized by the fact that the novel-configuration logic circuit can be easily manufactured in a bipolar process, having a high integration degree and allowing a high-speed operation. For standard longitudinal-type NPN transistor TR0, its emitter E0 is connected to bias terminal BIAS, base B0 is connected to voltage source+Vcc, and collector C0 is connected to base B1 of PNP transistor TR1. For lateral-type PNP transistor TR1, emitter E1 is connected to voltage source Vxx, base B1 is connected to both the collector Co of NPN transistor TR0 and input terminal IN, and collectors C1, C2, C3, . . . Cn are connected to output terminals OUT1, OUT2, PUT3, . . .OUTn, respectively. Schottky diodes SBD1, SBD2, SBD3, . . .SBDn are connected between base B1 and collectors C1, C2, C3, . . . Cn of NPN transistor TR1 with a cathode on the side of the base and with an anode on the side of the collector.
    Type: Grant
    Filed: May 24, 1993
    Date of Patent: March 28, 1995
    Assignee: Texas Instruments Incorporated
    Inventor: Shigeru Nakagawa
  • Patent number: 5333553
    Abstract: The carrier for linear motor vehicle-borne field magnets includes a aluminium profiled material of a gate shape in section, which is provided with recesses of permanent magnet size in both its legs. Permanent magnets attached to iron cores are inserted into the recesses in such a way that the N and S poles thereof are opposite to each other and alternate in the longitudinal direction of the carrier frame to form a spatial magnetic field by the alternation of the N and S poles between both the legs of the carrier frame, which interacts with the moving magnetic field created by ground-side coils to generate driving power. The carrier further includes support wheels, guide wheels and a vehicle support on which a vehicle is placed.
    Type: Grant
    Filed: November 12, 1993
    Date of Patent: August 2, 1994
    Assignees: East Japan Railway Company, Railway Technical Research Institute, Magnetic Transportation System Engineering Company
    Inventors: Kazumi Matsui, Kouichi Matsuoka, Shigeru Nakagawa
  • Patent number: 5071887
    Abstract: A polyurethane elastomer produced by reaction of a polyisocyanate with an amine-type polyol and another type polyol, the polyisocyanate being an isocyanurate-modified hexamethyelene diisocyanate; and the equivalent ratio of active hydrogen to isocyanate group to be reacted being in a range of from 0.8 to 1.6; and the ratio of the amine-type polyol to the another type polyol being in a range of from 10/90 to 100/0 by weight.
    Type: Grant
    Filed: February 15, 1990
    Date of Patent: December 10, 1991
    Assignee: Nippon Polyurethane Industry Co., Ltd.
    Inventors: Shigeru Nakagawa, Kiyofumi Murayama, Yukio Ohbuchi, Yamagata Tomoyuki