Patents by Inventor Shigetoshi Sugawa
Shigetoshi Sugawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9137469Abstract: Reset noise in pixels is removed. A solid-state imaging device includes pixels arranged in row and column directions, in which each of the pixels includes a charge-voltage conversion terminal for voltage-converting signal charges transferred from a photoelectric conversion element by a transfer means, and a first reset means for resetting a voltage at the charge-voltage conversion terminal; signal lines, each of which is connected to the pixels in each column; a scanning means for selecting one row among others; and constant current circuit elements for supplying constant current to the signal lines. In the device, within each selected row, each reset voltage at each charge-voltage conversion terminal and a converted voltage from transferred signal charges are read out to and stored in each signal line supplied with constant current by each constant current circuit element, and then output.Type: GrantFiled: June 12, 2014Date of Patent: September 15, 2015Assignees: TOHOKU UNIVERSITY, OLYMPUS CORPORATIONInventor: Shigetoshi Sugawa
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Patent number: 9083901Abstract: A solid-state image pickup device comprises for each pixel a photoelectric converter PD, an input terminal FD of a signal amplifier and a transfer switch TX for transferring an optical signal from the photoelectric converter to the input terminal. The device additionally comprises means for resetting the photoelectric converter by opening the transfer switch TX under a condition of holding the voltage of the input terminal FD to a fixed high level before storing the optical signal in the photoelectric converter PD. With this arrangement, any residual electric charge in the photoelectric converter can be eliminated without paying the cost of reducing the manufacturing yield and degrading the chip performance.Type: GrantFiled: January 13, 2012Date of Patent: July 14, 2015Assignee: CANON KABUSHIKI KAISHAInventors: Toru Koizumi, Shigetoshi Sugawa, Tetsunobu Kochi
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Publication number: 20150140690Abstract: There is provided an etching method for a semiconductor product. The semiconductor product having, on a substrate, an SiO2 layer, and an Si layer with a free surface and directly stacked on the SiO2 layer is prepared. The Si layer is etched. Etching is performed while supplying an etching solution from a side of the free surface using high-concentration fluonitric acid as the etching solution, and etching is continued by switching to fluonitric acid having a concentration lower than that of the fluonitric acid immediately before or after at least part of a surface of the SiO2 layer immediately under the Si layer is exposed.Type: ApplicationFiled: December 9, 2014Publication date: May 21, 2015Applicant: TOHOKU UNIVERSITYInventors: Takeshi Sakai, Tatsuro Yoshida, Kazuhiro Yoshikawa, Shigetoshi Sugawa
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Patent number: 9030582Abstract: A transistor (24) which acts as a load-current source for a source follower amplifying transistor (22) for outputting a pixel signal to a pixel output line (40) is provided in each picture element (10), whereby a high bias current is prevented from passing through the high-resistance pixel output line (40), so that a variation in an offset voltage among picture elements is suppressed. Inclusion of the high-resistance pixel output line (40) into the source follower amplification circuit is also avoided, whereby the gain characteristics are prevented from deterioration. Thus, the S/N ratio of the picture element is improved so as to enhance the quality of the images.Type: GrantFiled: February 8, 2011Date of Patent: May 12, 2015Assignees: Shimadzu Corporation, Tohoku UniversityInventors: Shigetoshi Sugawa, Hideki Tominaga, Kenji Takubo, Yasushi Kondo
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Patent number: 8988571Abstract: A pixel area with a two-dimensional array of pixels (10) each including a photodiode and a memory area (3a) on which memory sections for holding signals produced by the pixels for continuously recordable frames are separately provided on a semiconductor substrate. All the pixels simultaneously perform a photocharge storage operation, and the signals produced by the photocharge storage are extracted in parallel through mutually independent pixel output lines (14). In a plurality of memory sections connected to one pixel output line, a sample-and-hold transistor of a different memory section is turned on for each exposure cycle so as to sequentially hold signals in a capacitor of each memory section. After the continuous imaging is completed, all the pixel are sequentially read. Unlike CCD cameras, the present sensor does not simultaneously drive all the gate loads. Therefore, the sensor consumes less power yet can be driven at high speeds.Type: GrantFiled: September 4, 2008Date of Patent: March 24, 2015Assignees: Tohoku University, Shimadzu CorporationInventors: Shigetoshi Sugawa, Yasushi Kondo, Hideki Tominaga
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Patent number: 8963760Abstract: To obtain accurate digital data while using a successive approximation system when performing analog-to-digital conversion processing in a plurality of steps, an AD converter includes: a signal generation unit that generates a ramp voltage based on a count signal; a signal conversion unit including a circuit that holds an input signal voltage, a successive approximation capacitance group that outputs bias voltages according to a connection combination of capacitances having different capacitance values, and a unit that compares one of the ramp voltage and the bias voltage with the signal voltage; and a control unit generating a digital signal of the signal voltage based on a comparison result of the bias voltage and the comparison result of the ramp voltage while acquiring data for calibration of the capacitance group based on the connection combination and the ramp voltage.Type: GrantFiled: July 18, 2014Date of Patent: February 24, 2015Assignees: Tohoku University, Olympus Medical Systems Corp.Inventor: Shigetoshi Sugawa
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Publication number: 20150048239Abstract: A plurality of photodiodes arrayed in a one-dimensional form are divided into a plurality of groups. The structure of an antireflection coating is changed for each group so that all the surfaces of the photodiodes belonging to each group are covered with an antireflection coating having a transmittance characteristic which shows a maximum transmittance within a range of wavelengths of light to be received by those photodiodes. In particular, a SiO2 coating layer on the silicon substrate and an Al2O3 coating layer are common to all the photodiodes, while the structure of the upper layers are modified with respect to the wavelength. Within an ultraviolet wavelength region, the coating structure is more finely changed with respect to the wavelength. By such a design, the transmittance can be improved while making the best efforts to avoid a complex manufacturing process.Type: ApplicationFiled: March 26, 2013Publication date: February 19, 2015Applicants: TOHOKU UNIVERSITY, SHIMADZU CORPORATIONInventors: Hideki Tominaga, Ryuta Hirose, Kenji Takubo, Shigetoshi Sugawa, Rihito Kuroda
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Publication number: 20150029375Abstract: A solid-state image pickup apparatus including: two-dimensionally arrayed unit pixels, each including a PD performing optical-electrical conversion of an incident light; an FD and two output terminals provided for each of pixel groups, each including one or more unit pixels, the two output terminals being capable of outputting a noise signal and a signal-noise sum signal separately; first and second transfer lines to which the output terminals are connected in common and which are capable of holding noise signal voltage and signal-noise sum signal voltage, respectively; first switches arranged between the output terminals and the first transfer lines; second switches arranged between the output terminals and the second transfer lines; third and fourth switches provided for the transfer lines, respectively; and third and fourth transfer lines to which the transfer lines are connected in parallel via third and fourth switches, respectively.Type: ApplicationFiled: October 14, 2014Publication date: January 29, 2015Applicant: OLYMPUS MEDICAL SYSTEMS CORP.Inventors: Shigetoshi SUGAWA, Nana AKAHANE, Satoru ADACHI
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Publication number: 20150029376Abstract: A solid-state image pickup apparatus includes: two-dimensionally arrayed unit pixels, each including a PD performing optical-electrical conversion of an incident light; an FD and an output terminal provided for each of pixel groups, each including one or more pixels, the terminal being capable of outputting a noise signal and a signal-noise sum signal separately; first lines to which the terminals are connected in common and which are capable of holding voltages based on signals outputted from the terminals; second lines provided in parallel with the first lines and capable of holding a voltage; inter-transfer-line capacitive elements connecting the second lines and the first lines; a reset switch resetting each of the second lines to a reset voltage; a readout switch provided for each of the second lines; and a third line to which the second lines are connected in parallel via the readout switches, respectively.Type: ApplicationFiled: October 14, 2014Publication date: January 29, 2015Applicant: OLYMPUS MEDICAL SYSTEMS CORP.Inventors: Shigetoshi SUGAWA, Nana AKAHANE, Satoru ADACHI
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Publication number: 20140327800Abstract: To obtain accurate digital data while using a successive approximation system when performing analog-to-digital conversion processing in a plurality of steps, an AD converter includes: a signal generation unit that generates a ramp voltage based on a count signal; a signal conversion unit including a circuit that holds an input signal voltage, a successive approximation capacitance group that outputs bias voltages according to a connection combination of capacitances having different capacitance values, and a unit that compares one of the ramp voltage and the bias voltage with the signal voltage; and a control unit generating a digital signal of the signal voltage based on a comparison result of the bias voltage and the comparison result of the ramp voltage while acquiring data for calibration of the capacitance group based on the connection combination and the ramp voltage.Type: ApplicationFiled: July 18, 2014Publication date: November 6, 2014Inventor: Shigetoshi SUGAWA
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Publication number: 20140312399Abstract: A gate insulating film of a conventional semiconductor device is subjected to dielectric breakdown at a low electric field strength and thus its service life is short. This is because since the size of the asperity of at least one of a semiconductor layer-side interface and an electrode-side interface is large and, an electric field applied to the gate insulating film is locally concentrated and has a variation in its strength. This problem is solved by specifying the sizes of the asperities of both interfaces of the gate insulating film.Type: ApplicationFiled: November 16, 2012Publication date: October 23, 2014Applicant: TOHOKU UNIVERSITYInventors: Rihito Kuroda, Akinobu Teramoto, Shigetoshi Sugawa
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Publication number: 20140306344Abstract: There is provided with a wiring structure. The wiring stracture has a damascene wiring structure including a metal wiring. The metal wiring is provided in direct contact with an upper surface of a barrier film (SiC(O, N) film) containing silicon (Si), carbon (C), and at least one of oxygen (O) and nitrogen (N) as constituent components.Type: ApplicationFiled: June 24, 2014Publication date: October 16, 2014Applicant: Tohoku UniversityInventors: Shigetoshi Sugawa, Akinobu Teramoto, Rihito Kuroda, Gu Xun
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Publication number: 20140291485Abstract: To remove reset noise in pixels while the circuit configuration is kept in low power consumption, a device includes pixels arranged in row and column directions, in which each of the pixels includes a charge-voltage conversion terminal for voltage-converting signal charges transferred from a photoelectric conversion element, and a first reset means for resetting a voltage at the charge-voltage conversion terminal; first signal lines, each of which is connected to the pixels in each column; a scanning means for selecting one row among others; and a second reset means for resetting voltages at the signal lines. In the device, on each selected row, by voltage signals at the charge-voltage conversion terminals and the converted voltage signals from the transferred signal charges are read out to and stored in the signal lines in a floating potential state, and then are output.Type: ApplicationFiled: June 12, 2014Publication date: October 2, 2014Inventor: Shigetoshi SUGAWA
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Publication number: 20140293105Abstract: Reset noise in pixels is removed. A solid-state imaging device includes pixels arranged in row and column directions, in which each of the pixels includes a charge-voltage conversion terminal for voltage-converting signal charges transferred from a photoelectric conversion element by a transfer means, and a first reset means for resetting a voltage at the charge-voltage conversion terminal; signal lines, each of which is connected to the pixels in each column; a scanning means for selecting one row among others; and constant current circuit elements for supplying constant current to the signal lines. In the device, within each selected row, each reset voltage at each charge-voltage conversion terminal and a converted voltage from transferred signal charges are read out to and stored in each signal line supplied with constant current by each constant current circuit element, and then output.Type: ApplicationFiled: June 12, 2014Publication date: October 2, 2014Inventor: Shigetoshi SUGAWA
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Publication number: 20140256065Abstract: There is provided an etching method. A temperature at a plurality of predetermined positions on an upper surface of an Si substrate is measured during the etching processing. The etching processing includes supplying an etching solution to the upper surface of the Si substrate. An exothermic reaction occurs in the etching processing. The upper surface is heated or cooled depending on the measured value.Type: ApplicationFiled: May 20, 2014Publication date: September 11, 2014Applicant: Tohoku UniversityInventors: Takeshi Sakai, Tatsuro Yoshida, Kazuhiro Yoshikawa, Shigetoshi Sugawa
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Publication number: 20140106496Abstract: A method of manufacturing an active pixel sensor having a plurality of pixels, each of the pixels having a photodiode formed by a part of a first semiconductor region of a first conductive type and a second semiconductor region of a second conductive type, and a transfer transistor for transferring a charge carrier from the photodiode, includes the steps of preparing a substrate on which the first semiconductor region of the first conductive type is formed, forming a mask to form the second semiconductor region on the substrate, forming the second semiconductor region using the mask, and forming a gate of the transferring transistor after forming the second semiconductor region. The gate of the transferring transistor overlaps the second semiconductor region in a planar view.Type: ApplicationFiled: December 23, 2013Publication date: April 17, 2014Applicant: CANON KABUSHIKI KAISHAInventors: Toru Koizumi, Shigetoshi Sugawa, Isamu Ueno, Tetsunobu Kochi, Katsuhito Sakurai, Hiroki Hiyama
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Publication number: 20140097510Abstract: Provided is a photodiode having a high-concentration layer on its surface, in which the high-concentration layer is formed so that the thickness of a non-depleted region is larger than the roughness of an interface between silicon and an insulator layer, and is smaller than a penetration depth of ultraviolet light.Type: ApplicationFiled: June 4, 2012Publication date: April 10, 2014Applicants: SHIMADZU CORPORATION, TOHOKU UNIVERSITYInventors: Shigetoshi Sugawa, Rihito Kuroda
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Patent number: 8633395Abstract: A multilayer wiring board 100 comprises a first wiring region 101 where wirings 103a and insulating layers 104a and 104b are alternately laminated, and a second wiring region 102 where a thickness H2 of an insulating layer 104 is twice or more a thickness H1 of the insulating layer in the first wiring region 101 and a width W2 of a wiring 103b is twice or more a width W1 of the wiring in the first wiring region 101. The first wiring region 101 and the second wiring region 102 are integrally formed on the same board.Type: GrantFiled: May 22, 2009Date of Patent: January 21, 2014Assignees: National University Corporation Tohoku University, Foundation For Advancement of International ScienceInventors: Tadahiro Ohmi, Shigetoshi Sugawa, Hiroshi Imai, Akinobu Teramoto
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Publication number: 20130320477Abstract: A method of etching capable of rapidly and flatly performing wet etching on a Si substrate using fluonitric acid represented by HF(a)HNO3(b)H2O(c) (where the unit of a, b and c is wt % and a+b+c=100). The etching rate of an SiO2 layer with the highly concentrated fluonitric acid is significantly lowered by the appropriate selection of its composition as compared with the etching rate of the Si substrate, and etch the Si substrate until the SiO2 layer is exposed. In this way, it is possible to rapidly etch the Si substrate and significantly enhance the flatness of the etched surface.Type: ApplicationFiled: October 28, 2011Publication date: December 5, 2013Applicant: TOHOKU UNIVERSITYInventors: Tadahiro Ohmi, Tomotsugu Ohashi, Kazuhiro Yoshikawa, Tatsuro Yoshida, Teppei Uchimura, Kazuki Soeda, Shigetoshi Sugawa
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Publication number: 20130308023Abstract: A transistor (24) which acts as a load-current source for a source follower amplifying transistor (22) for outputting a pixel signal to a pixel output line (40) is provided in each picture element (10), whereby a high bias current is prevented from passing through the high-resistance pixel output line (40), so that a variation in an offset voltage among picture elements is suppressed. Inclusion of the high-resistance pixel output line (40) into the source follower amplification circuit is also avoided, whereby the gain characteristics are prevented from deterioration. Thus, the S/N ratio of the picture element is improved so as to enhance the quality of the images.Type: ApplicationFiled: February 8, 2011Publication date: November 21, 2013Applicants: Shimadzu Corporation, Tohoku UniversityInventors: Shigetoshi Sugawa, Hideki Tominaga, Kenji Takubo, Yasushi Kondo