Patents by Inventor Shigeyuki Ueda
Shigeyuki Ueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11037897Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.Type: GrantFiled: November 14, 2019Date of Patent: June 15, 2021Assignee: Rohm Co., Ltd.Inventors: Tadahiro Morifuji, Shigeyuki Ueda
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Patent number: 10761700Abstract: A display device includes: a display; a touch panel disposed on the display; a memory that stores screen configuration information essentially including information of a base area of a fixed size and an extra area of an unfixed size; a retrieving portion that retrieves the screen configuration information therefrom; a display processor that allocates the base area in an image displayable area of the display on the basis of a reference point of the screen of the display and displays a first screen in the allocated base area, and that further allocates the extra area in an area other than the base area and displays a second screen in the allocated extra area when the image displayable area of the display is larger than the base area; and a judgment portion that judges whether or not a user stretches the extra area toward the base area on the touch panel.Type: GrantFiled: December 1, 2016Date of Patent: September 1, 2020Assignee: KONICA MINOLTA, INC.Inventors: Masao Hosono, Shigeyuki Ueda, Tadashi Suzue, Satoshi Osako
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Publication number: 20200098713Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.Type: ApplicationFiled: November 14, 2019Publication date: March 26, 2020Applicant: Rohm Co., Ltd.Inventors: Tadahiro Morifuji, Shigeyuki Ueda
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Patent number: 10510700Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.Type: GrantFiled: June 26, 2018Date of Patent: December 17, 2019Assignee: Rohm Co., Ltd.Inventors: Tadahiro Morifuji, Shigeyuki Ueda
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Patent number: 10412251Abstract: An image processing apparatus includes a host controller that controls a hardware resource, a guest controller, an emulator that is provided between the host controller and the guest controller and allows the guest controller to control the hardware resource, and a changer that changes an HDL program, wherein the guest controller includes a guest driver, the emulator includes a device emulator that emulates the hardware resource by executing the changed HDL program, and a switcher that switches control to any one of a first control for controlling the host controller in accordance with control of the hardware resource by the guest driver and allowing the hardware resource to be controlled, and a second control for controlling the device emulator in accordance with the control of the hardware resource by the guest driver.Type: GrantFiled: June 15, 2017Date of Patent: September 10, 2019Assignee: Konica Minolta, Inc.Inventors: Satoshi Osako, Shigeyuki Ueda, Masao Hosono
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Publication number: 20180301429Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.Type: ApplicationFiled: June 26, 2018Publication date: October 18, 2018Inventors: Tadahiro Morifuji, Shigeyuki Ueda
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Patent number: 10104255Abstract: An information processing apparatus, which can communicate with other information processing apparatuses, includes: a volatile storage; a nonvolatile storage; a storage controller that associates data with a user and stores the data; a data manager that shares management information with the other information processing apparatuses; an operation user detector that detects a user operating any of the apparatuses as an operation user; an operation state switcher that switches between a first operation and a second operation state; a data specifier that specifies data related to the operation user and an apparatus stored with the data; a data obtainer that obtains data from a storage device; a transferer that stores data stored in the nonvolatile storage among the specified data in the volatile storage; and a data supplier that returns data specified by a request among the data stored in the second or the volatile storage.Type: GrantFiled: December 15, 2017Date of Patent: October 16, 2018Assignee: Konica Minolta, Inc.Inventor: Shigeyuki Ueda
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Patent number: 10032739Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.Type: GrantFiled: May 10, 2017Date of Patent: July 24, 2018Assignee: Rohm Co., Ltd.Inventors: Tadahiro Morifuji, Shigeyuki Ueda
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Publication number: 20180176403Abstract: An information processing apparatus, which can communicate with other information processing apparatuses, includes: a volatile storage; a nonvolatile storage; a storage controller that associates data with a user and stores the data; a data manager that shares management information with the other information processing apparatuses; an operation user detector that detects a user operating any of the apparatuses as an operation user; an operation state switcher that switches between a first operation and a second operation state; a data specifier that specifies data related to the operation user and an apparatus stored with the data; a data obtainer that obtains data from a storage device; a transferer that stores data stored in the nonvolatile storage among the specified data in the volatile storage; and a data supplier that returns data specified by a request among the data stored in the second or the volatile storage.Type: ApplicationFiled: December 15, 2017Publication date: June 21, 2018Applicant: Konica Minolta, Inc.Inventor: Shigeyuki Ueda
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Patent number: 9983839Abstract: An image processing apparatus includes a volatile first storage, a non-volatile second storage, a host controller, a guest controller, an emulator that emulates access to the first storage and the second storage by the host controller such that the guest controller accesses the first storage and the second storage, and an application portion that controls the host controller to access the first storage and the second storage. Any one of the application portion and the emulator includes a transfer portion that stores data that is stored in a predetermined region of the second storage in a certain region of the first storage before the application portion stops the second storage. The emulator includes an access destination converter that converts access to the second storage by the guest controller into access to the certain region of the first storage after the second storage is stopped.Type: GrantFiled: June 13, 2017Date of Patent: May 29, 2018Assignee: Konica Minolta, Inc.Inventors: Masao Hosono, Shigeyuki Ueda, Tadashi Suzue
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Patent number: 9880791Abstract: An image formation apparatus includes a hypervisor, a control firmware running on a host OS and responsible for controlling the image formation apparatus, and a cooperation module operating on the same level as the hypervisor. A resource includes an image memory managed by the control firmware and adapted for image processing. The cooperation module is configured to: cooperate with the control firmware to obtain an available memory space of the image memory; associate a content of a job to be processed with a program running on one or more guest OSs required for that job; and before starting the job, read a required guest OS into the available memory space of the image memory and cause the associated program to be executed.Type: GrantFiled: December 12, 2016Date of Patent: January 30, 2018Assignee: KONICA MINOLTA, INC.Inventors: Tadashi Suzue, Shigeyuki Ueda, Masao Hosono, Satoshi Osako
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Publication number: 20170374219Abstract: An image processing apparatus includes a host controller that controls a hardware resource, a guest controller, an emulator that is provided between the host controller and the guest controller and allows the guest controller to control the hardware resource, and a changer that changes an HDL program, wherein the guest controller includes a guest driver, the emulator includes a device emulator that emulates the hardware resource by executing the changed HDL program, and a switcher that switches control to any one of a first control for controlling the host controller in accordance with control of the hardware resource by the guest driver and allowing the hardware resource to be controlled, and a second control for controlling the device emulator in accordance with the control of the hardware resource by the guest driver.Type: ApplicationFiled: June 15, 2017Publication date: December 28, 2017Applicant: Konica Minolta, Inc.Inventors: Satoshi OSAKO, Shigeyuki UEDA, Masao HOSONO
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Publication number: 20170357471Abstract: An image processing apparatus includes a volatile first storage, a non-volatile second storage, a host controller, a guest controller, an emulator that emulates access to the first storage and the second storage by the host controller such that the guest controller accesses the first storage and the second storage, and an application portion that controls the host controller to access the first storage and the second storage. Any one of the application portion and the emulator includes a transfer portion that stores data that is stored in a predetermined region of the second storage in a certain region of the first storage before the application portion stops the second storage. The emulator includes an access destination converter that converts access to the second storage by the guest controller into access to the certain region of the first storage after the second storage is stopped.Type: ApplicationFiled: June 13, 2017Publication date: December 14, 2017Applicant: Konica Minolta, Inc.Inventors: Masao Hosono, Shigeyuki Ueda, Tadashi Suzue
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Patent number: 9756938Abstract: A storage device includes, in a box having an open front, a rotation mechanism section that rotatably holds a storage body that stores an object and is rotatable about a shaft extending along an up-down direction. The rotation mechanism section includes: a stationary rail affixed to a top surface of the box and including a guide groove open downward and forward and extending in a front-back direction and a guide body on a holding section protruding downward from a groove bottom surface of the guide groove; and a movable rail movable in the front-back direction along the guide groove in the stationary rail, coupled to the storage body via the shaft, and including: left and right sidewalls, a bottom wall, and a front end wall that define a receiving groove for receiving the guide body; and a top wall that forms a slit opening for receiving the holding section.Type: GrantFiled: June 19, 2015Date of Patent: September 12, 2017Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventor: Shigeyuki Ueda
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Publication number: 20170243844Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.Type: ApplicationFiled: May 10, 2017Publication date: August 24, 2017Inventors: Tadahiro Morifuji, Shigeyuki Ueda
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Patent number: 9685419Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.Type: GrantFiled: July 26, 2016Date of Patent: June 20, 2017Assignee: Rohm Co., Ltd.Inventors: Tadahiro Morifuji, Shigeyuki Ueda
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Publication number: 20170168758Abstract: An image formation apparatus includes a hypervisor, a control firmware running on a host OS and responsible for controlling the image formation apparatus, and a cooperation module operating on the same level as the hypervisor. A resource includes an image memory managed by the control firmware and adapted for image processing. The cooperation module is configured to: cooperate with the control firmware to obtain an available memory space of the image memory; associate a content of a job to be processed with a program running on one or more guest OSs required for that job; and before starting the job, read a required guest OS into the available memory space of the image memory and cause the associated program to be executed.Type: ApplicationFiled: December 12, 2016Publication date: June 15, 2017Applicant: Konica Minolta, Inc.Inventors: Tadashi Suzue, Shigeyuki Ueda, Masao Hosono, Satoshi Osako
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Publication number: 20170160912Abstract: A display device includes: a display; a touch panel disposed on the display; a memory that stores screen configuration information essentially including information of a base area of a fixed size and an extra area of an unfixed size; a retrieving portion that retrieves the screen configuration information therefrom; a display processor that allocates the base area in an image displayable area of the display on the basis of a reference point of the screen of the display and displays a first screen in the allocated base area, and that further allocates the extra area in an area other than the base area and displays a second screen in the allocated extra area when the image displayable area of the display is larger than the base area; and a judgment portion that judges whether or not a user stretches the extra area toward the base area on the touch panel.Type: ApplicationFiled: December 1, 2016Publication date: June 8, 2017Applicant: KONICA MINOLTA, INC.Inventors: Masao HOSONO, Shigeyuki UEDA, Tadashi SUZUE, Satoshi OSAKO
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Patent number: D818292Type: GrantFiled: January 16, 2017Date of Patent: May 22, 2018Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Masaya Yoshioka, Shigeyuki Ueda
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Patent number: D920771Type: GrantFiled: December 12, 2019Date of Patent: June 1, 2021Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventor: Shigeyuki Ueda