Abstract: A storage device includes, in a box having an open front, a rotation mechanism section that rotatably holds a storage body that stores an object and is rotatable about a shaft extending along an up-down direction. The rotation mechanism section includes: a stationary rail affixed to a top surface of the box and including a guide groove open downward and forward and extending in a front-back direction and a guide body on a holding section protruding downward from a groove bottom surface of the guide groove; and a movable rail movable in the front-back direction along the guide groove in the stationary rail, coupled to the storage body via the shaft, and including: left and right sidewalls, a bottom wall, and a front end wall that define a receiving groove for receiving the guide body; and a top wall that forms a slit opening for receiving the holding section.

Abstract: An image generation apparatus includes: a touch panel; an enlarged display unit that enlarges an image within a predetermined range from a touch position and overlaps the enlarged image with an original screen display on a display screen of the touch panel; an acceptance unit that accepts a button operation within an enlarged display area; and a correspondence display unit that produces a correspondence display with correspondence between a button displayed in the enlarged display area and a non-enlarged portion of the button.

Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.

Abstract: A semiconductor chip includes an electrode pad on a substrate, a barrier metal layer on the electrode pad, a bump electrode, a first protection layer formed on the substrate, and a second protection layer having an opening. The first protection layer overlaps part of the electrode pad. The second protection layer covers a region over the first protection layer and a region over the electrode pad. The upper surface of the second protection layer has an arc surface. The thickness between the arc surface and the electrode pad as seen in a sectional view is gradually large from the rim of the opening to the rim of the electrode pad. The rate of change of the thickness is higher at the rim of the opening than at the rim of the electrode pad.

Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.

Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.

Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.

Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.

Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.

Abstract: An image processing method, an image processing apparatus and an image capturing apparatus are provided, which are capable of obtaining an output image exhibiting high visual recognizability while reducing the processing time with a circuit on a comparatively small scale.

Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.

Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.

Abstract: An image processing method, an image processing apparatus and an image capturing apparatus are provided, which are capable of obtaining an output image exhibiting high visual recognizability while reducing the processing time with a circuit on a comparatively small scale.

Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion formed on the upper surface of a semiconductor substrate, a passivation layer so formed on the upper surface of the semiconductor substrate as to overlap a part of the electrode pad portion and having a first opening portion where the upper surface of the electrode pad portion is exposed, a barrier metal layer formed on the electrode pad portion, and a solder bump formed on the barrier metal layer. The barrier metal layer is formed such that an outer peripheral end lies within the first opening portion of the passivation layer when viewed in plan.

Abstract: An image processing apparatus is provided which makes it possible to improve an access speed for accessing a storage device so as to improve an image processing velocity without increasing a capacity of the storage device. The apparatus includes an optical system; an imaging device having a plurality of pixels each corresponding to one of colors and an arithmetic calculating section to process image data. When a color of an original pixel is different from that of a distortion-corrected pixel, the arithmetic calculating section conducts an interpolation processing to calculate pixel data of the distortion-corrected pixel from other pixel data of plural pixels residing at peripheral positions surrounding the original pixel, stored in advance, and the arithmetic calculating section stores pixel data categorized in one of the colors as a continuous series of the pixel data into corresponding one of storing areas provided in the storage section.

Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.

Abstract: A semiconductor chip in which a through hole penetrating through its surface and reverse surface is formed in a scribe line region in the vicinity of an active region where a functional device is formed, and a conductive member is arranged in the through portion. The through portion may be a groove opening sideward on a sidewall surface of the semiconductor chip. The through portion may be a through hole blocked from a side part of the semiconductor chip. The semiconductor chip may further include wiring for electrically connecting an internal circuit formed in the active region and the conductive member to each other.

Abstract: A semiconductor chip having a functional bump provided on a surface of a semiconductor substrate thereof for electrical connection between an internal circuit thereof and a solid device, and a dummy bump not serving for the electrical connection between the internal circuit and the solid device. The dummy bump may be a stress relieving bump for relieving stresses exerted thereon. The dummy bump may be connected to a low impedance portion. The functional bump and the dummy bump may be provided on a surface protective film. In this case, the dummy bump is provided on a recess formed in the surface protective film.

Abstract: A semiconductor chip which is to be overlapped with and joined to a surface of another solid device. The semiconductor chip has a surface protective film for covering internal wiring, an external connection pad which is formed by partially exposing the internal wiring from the surface protective film, and a wire connecting portion which is formed using a metal material having oxidation resistance on the external connection pad and to which a wire for electrical connection to an external terminal is connected. It is preferable that the semiconductor chip further has an internal connection pad used for connection to the solid device and a bump formed on the pad.

Abstract: A production process for a semiconductor device having a metal electrode on a semiconductor substrate thereof. A metal electrode portion is formed on a surface of another substrate for electrode transfer. Then, the metal electrode portion is transferred from the electrode transfer substrate onto the semiconductor substrate by pressing together the electrode transfer substrate and the semiconductor substrate. The electrode transfer substrate has, for example, a seed film provided on the surface thereof, and the formation of the metal electrode portion on the electrode transfer substrate may be achieved by depositing a material for the metal electrode on the seed film by plating. The electrode transfer substrate may have an insulating film which covers a surface of the seed film except a portion thereof on which the metal electrode portion is to be formed.